Florent Kermarrec 9547938527 bios/sdram: changes to ease manual read window selection		2018-08-18 13:45:22 +02:00
..
cores	cpu/lm32: add minimal variant with no i/d cache, pipelined barrel shifter and multiplier (useful to build SoC on small FPGAs like ice40)	2018-08-17 08:32:32 +02:00
integration	cpu_interace: use riscv64-unknown-elf if available else riscv32-unknown-elf	2018-08-16 10:04:09 +02:00
interconnect	soc/interconnect/wishbone: add Timeout to avoid stalling bus when not responding and generate error.	2018-08-06 12:21:18 +02:00
software	bios/sdram: changes to ease manual read window selection	2018-08-18 13:45:22 +02:00
tools	litex_server: allow multiple clients to connect to the same server	2018-08-17 16:09:08 +02:00
__init__.py
MISOC_LICENSE