mirror of
https://github.com/enjoy-digital/litex.git
synced 2025-01-04 09:52:26 -05:00
fb145daced
This program is no longer needed. The `openocd_vexriscv` package natively supports `etherbone`, and now that the vexriscv debug module is available on Wishbone instead of as a CSR, this module no longer works. This change simplifies both tooling (because there is one fewer program to run) and integration (because you don't need to modify your CSRs anymore, just `register_mem()`.) Signed-off-by: Sean Cross <sean@xobs.io>
44 lines
1.3 KiB
Python
Executable file
44 lines
1.3 KiB
Python
Executable file
#!/usr/bin/env python3
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import sys
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from setuptools import setup
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from setuptools import find_packages
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if sys.version_info[:3] < (3, 5):
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raise SystemExit("You need Python 3.5+")
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setup(
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name="litex",
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version="0.2.dev",
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description="Python tools to design FPGA cores and SoCs",
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long_description=open("README").read(),
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author="Florent Kermarrec",
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author_email="florent@enjoy-digital.fr",
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url="http://enjoy-digital.fr",
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download_url="https://github.com/enjoy-digital/litex",
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test_suite="test",
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license="BSD",
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platforms=["Any"],
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keywords="HDL ASIC FPGA hardware design",
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classifiers=[
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"Topic :: Scientific/Engineering :: Electronic Design Automation (EDA)",
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"Environment :: Console",
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"Development Status :: Alpha",
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"Intended Audience :: Developers",
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"License :: OSI Approved :: BSD License",
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"Operating System :: OS Independent",
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"Programming Language :: Python",
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],
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packages=find_packages(exclude=("test*", "sim*", "doc*")),
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install_requires=["pyserial"],
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include_package_data=True,
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entry_points={
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"console_scripts": [
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"litex_term=litex.soc.tools.litex_term:main",
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"mkmscimg=litex.soc.tools.mkmscimg:main",
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"litex_server=litex.soc.tools.remote.litex_server:main"
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],
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},
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)
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