187 lines
7.0 KiB
Python
187 lines
7.0 KiB
Python
from mibuild.generic_platform import *
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from mibuild.xilinx import XilinxPlatform
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from mibuild.xilinx.programmer import UrJTAG
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_io = [
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("user_led", 0, Pins("V5"), IOStandard("LVCMOS33"), Drive(24), Misc("SLEW=QUIETIO")),
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("clk50", 0, Pins("AB13"), IOStandard("LVCMOS33")),
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# When executing softcore code in-place from the flash, we want
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# the flash reset to be released before the system reset.
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("norflash_rst_n", 0, Pins("P22"), IOStandard("LVCMOS33"), Misc("SLEW=FAST"), Drive(8)),
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("norflash", 0,
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Subsignal("adr", Pins("L22 L20 K22 K21 J19 H20 F22",
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"F21 K17 J17 E22 E20 H18 H19 F20",
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"G19 C22 C20 D22 D21 F19 F18 D20 D19")),
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Subsignal("d", Pins("AA20 U14 U13 AA6 AB6 W4 Y4 Y7",
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"AA2 AB2 V15 AA18 AB18 Y13 AA12 AB12"), Misc("PULLDOWN")),
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Subsignal("oe_n", Pins("M22")),
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Subsignal("we_n", Pins("N20")),
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Subsignal("ce_n", Pins("M21")),
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IOStandard("LVCMOS33"), Misc("SLEW=FAST"), Drive(8)
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),
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("serial", 0,
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Subsignal("tx", Pins("L17"), IOStandard("LVCMOS33"), Misc("SLEW=SLOW")),
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Subsignal("rx", Pins("K18"), IOStandard("LVCMOS33"), Misc("PULLUP"))
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),
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("ddram_clock", 0,
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Subsignal("p", Pins("M3")),
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Subsignal("n", Pins("L4")),
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IOStandard("SSTL2_I")
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),
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("ddram", 0,
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Subsignal("a", Pins("B1 B2 H8 J7 E4 D5 K7 F5 G6 C1 C3 D1 D2")),
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Subsignal("ba", Pins("A2 E6")),
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Subsignal("cs_n", Pins("F7")),
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Subsignal("cke", Pins("G7")),
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Subsignal("ras_n", Pins("E5")),
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Subsignal("cas_n", Pins("C4")),
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Subsignal("we_n", Pins("D3")),
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Subsignal("dq", Pins("Y2 W3 W1 P8 P7 P6 P5 T4 T3",
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"U4 V3 N6 N7 M7 M8 R4 P4 M6 L6 P3 N4",
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"M5 V2 V1 U3 U1 T2 T1 R3 R1 P2 P1")),
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Subsignal("dm", Pins("E1 E3 F3 G4")),
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Subsignal("dqs", Pins("F1 F2 H5 H6")),
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IOStandard("SSTL2_I")
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),
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("eth_clocks", 0,
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Subsignal("phy", Pins("M20")),
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Subsignal("rx", Pins("H22")),
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Subsignal("tx", Pins("H21")),
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IOStandard("LVCMOS33")
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),
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("eth", 0,
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Subsignal("rst_n", Pins("R22")),
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Subsignal("dv", Pins("V21")),
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Subsignal("rx_er", Pins("V22")),
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Subsignal("rx_data", Pins("U22 U20 T22 T21")),
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Subsignal("tx_en", Pins("N19")),
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Subsignal("tx_er", Pins("M19")),
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Subsignal("tx_data", Pins("M16 L15 P19 P20")),
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Subsignal("col", Pins("W20")),
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Subsignal("crs", Pins("W22")),
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IOStandard("LVCMOS33")
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),
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("vga_out", 0,
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Subsignal("clk", Pins("A10")),
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Subsignal("r", Pins("C6 B6 A6 C7 A7 B8 A8 D9")),
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Subsignal("g", Pins("C8 C9 A9 D7 D8 D10 C10 B10")),
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Subsignal("b", Pins("D11 C12 B12 A12 C13 A13 D14 C14")),
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Subsignal("hsync_n", Pins("A14")),
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Subsignal("vsync_n", Pins("C15")),
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Subsignal("psave_n", Pins("B14")),
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IOStandard("LVCMOS33")
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),
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("dvi_out", 0,
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Subsignal("clk_p", Pins("W12"), IOStandard("TMDS_33")),
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Subsignal("clk_n", Pins("Y12"), IOStandard("TMDS_33")),
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Subsignal("data0_p", Pins("Y16"), IOStandard("TMDS_33")),
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Subsignal("data0_n", Pins("W15"), IOStandard("TMDS_33")),
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Subsignal("data1_p", Pins("AA16"), IOStandard("TMDS_33")),
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Subsignal("data1_n", Pins("AB16"), IOStandard("TMDS_33")),
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Subsignal("data2_p", Pins("Y15"), IOStandard("TMDS_33")),
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Subsignal("data2_n", Pins("AB15"), IOStandard("TMDS_33")),
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),
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("mmc", 0,
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Subsignal("clk", Pins("J3")),
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Subsignal("cmd", Pins("K1")),
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Subsignal("dat", Pins("J6 K6 N1 K5")),
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IOStandard("LVCMOS33")
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),
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("dvi_in", 0,
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Subsignal("clk_p", Pins("K20"), IOStandard("TMDS_33")),
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Subsignal("clk_n", Pins("K19"), IOStandard("TMDS_33")),
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Subsignal("data0_p", Pins("B21"), IOStandard("TMDS_33")),
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Subsignal("data0_n", Pins("B22"), IOStandard("TMDS_33")),
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Subsignal("data1_p", Pins("A20"), IOStandard("TMDS_33")),
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Subsignal("data1_n", Pins("A21"), IOStandard("TMDS_33")),
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Subsignal("data2_p", Pins("K16"), IOStandard("TMDS_33")),
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Subsignal("data2_n", Pins("J16"), IOStandard("TMDS_33")),
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Subsignal("scl", Pins("G20"), IOStandard("LVCMOS33")),
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Subsignal("sda", Pins("H16"), IOStandard("LVCMOS33")),
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Subsignal("hpd_notif", Pins("G22"), IOStandard("LVCMOS33")),
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Subsignal("hpd_en", Pins("G17"), IOStandard("LVCMOS33"))
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),
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("dvi_in", 1,
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Subsignal("clk_p", Pins("C11"), IOStandard("TMDS_33")),
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Subsignal("clk_n", Pins("A11"), IOStandard("TMDS_33")),
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Subsignal("data0_p", Pins("B18"), IOStandard("TMDS_33")),
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Subsignal("data0_n", Pins("A18"), IOStandard("TMDS_33")),
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Subsignal("data1_p", Pins("C17"), IOStandard("TMDS_33")),
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Subsignal("data1_n", Pins("A17"), IOStandard("TMDS_33")),
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Subsignal("data2_p", Pins("E16"), IOStandard("TMDS_33")),
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Subsignal("data2_n", Pins("D17"), IOStandard("TMDS_33")),
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Subsignal("scl", Pins("F17"), IOStandard("LVCMOS33")),
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Subsignal("sda", Pins("F16"), IOStandard("LVCMOS33")),
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Subsignal("hpd_notif", Pins("G16"), IOStandard("LVCMOS33")),
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Subsignal("hpd_en", Pins("B20"), IOStandard("LVCMOS33"))
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),
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("dvi_in", 2,
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Subsignal("clk_p", Pins("Y11"), IOStandard("TMDS_33")),
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Subsignal("clk_n", Pins("AB11"), IOStandard("TMDS_33")),
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Subsignal("data0_p", Pins("V11"), IOStandard("TMDS_33")),
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Subsignal("data0_n", Pins("W11"), IOStandard("TMDS_33")),
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Subsignal("data1_p", Pins("AA10"), IOStandard("TMDS_33")),
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Subsignal("data1_n", Pins("AB10"), IOStandard("TMDS_33")),
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Subsignal("data2_p", Pins("R11"), IOStandard("TMDS_33")),
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Subsignal("data2_n", Pins("T11"), IOStandard("TMDS_33")),
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Subsignal("scl", Pins("C16"), IOStandard("LVCMOS33")),
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Subsignal("sda", Pins("B16"), IOStandard("LVCMOS33")),
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Subsignal("hpd_notif", Pins("D6"), IOStandard("LVCMOS33")),
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Subsignal("hpd_en", Pins("A4"), IOStandard("LVCMOS33"))
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),
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("dvi_in", 3,
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Subsignal("clk_p", Pins("J20"), IOStandard("TMDS_33")),
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Subsignal("clk_n", Pins("J22"), IOStandard("TMDS_33")),
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Subsignal("data0_p", Pins("P18"), IOStandard("TMDS_33")),
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Subsignal("data0_n", Pins("R19"), IOStandard("TMDS_33")),
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Subsignal("data1_p", Pins("P17"), IOStandard("TMDS_33")),
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Subsignal("data1_n", Pins("N16"), IOStandard("TMDS_33")),
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Subsignal("data2_p", Pins("M17"), IOStandard("TMDS_33")),
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Subsignal("data2_n", Pins("M18"), IOStandard("TMDS_33")),
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Subsignal("scl", Pins("P21"), IOStandard("LVCMOS33")),
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Subsignal("sda", Pins("N22"), IOStandard("LVCMOS33")),
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Subsignal("hpd_notif", Pins("H17"), IOStandard("LVCMOS33")),
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Subsignal("hpd_en", Pins("C19"), IOStandard("LVCMOS33"))
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),
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]
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class Platform(XilinxPlatform):
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identifier = 0x4D58
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default_clk_name = "clk50"
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default_clk_period = 20
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def __init__(self):
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XilinxPlatform.__init__(self, "xc6slx45-fgg484-2", _io)
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self.add_platform_command("CONFIG VCCAUX=\"3.3\";\n")
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def create_programmer(self):
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return UrJTAG("fjmem-mixxeo.bit")
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def do_finalize(self, fragment):
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XilinxPlatform.do_finalize(self, fragment)
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try:
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eth_clocks = self.lookup_request("eth_clocks")
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self.add_period_constraint(eth_clocks.rx, 40)
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self.add_period_constraint(eth_clocks.tx, 40)
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self.add_platform_command("""
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TIMESPEC "TS{phy_tx_clk}_io" = FROM "GRP{phy_tx_clk}" TO "PADS" 10 ns;
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TIMESPEC "TS{phy_rx_clk}_io" = FROM "PADS" TO "GRP{phy_rx_clk}" 10 ns;
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""", phy_rx_clk=eth_clocks.rx, phy_tx_clk=eth_clocks.tx)
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except ConstraintError:
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pass
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for i in range(4):
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try:
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self.add_period_constraint(self.lookup_request("dvi_in", i).clk_p, 12)
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except ConstraintError:
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pass
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