mirror of
https://github.com/enjoy-digital/litex.git
synced 2025-01-04 09:52:26 -05:00
0f8f89a269
- data seems stable (mila capture) except when receive the ALIGN primtive from the device, we should maybe disable alignment on the HOST when link is ready...
144 lines
4.6 KiB
Python
144 lines
4.6 KiB
Python
from mibuild.generic_platform import *
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from mibuild.crg import SimpleCRG
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from mibuild.xilinx_common import CRG_DS
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from mibuild.xilinx_ise import XilinxISEPlatform
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from mibuild.xilinx_vivado import XilinxVivadoPlatform
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from mibuild.programmer import *
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def _run_vivado(cmds):
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with subprocess.Popen("vivado -mode tcl", stdin=subprocess.PIPE, shell=True) as process:
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process.stdin.write(cmds.encode("ASCII"))
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process.communicate()
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class VivadoProgrammer(Programmer):
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needs_bitreverse = False
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def load_bitstream(self, bitstream_file):
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cmds = """open_hw
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connect_hw_server
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open_hw_target [lindex [get_hw_targets -of_objects [get_hw_servers localhost]] 0]
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set_property PROBES.FILE {{}} [lindex [get_hw_devices] 0]
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set_property PROGRAM.FILE {{{bitstream}}} [lindex [get_hw_devices] 0]
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program_hw_devices [lindex [get_hw_devices] 0]
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refresh_hw_device [lindex [get_hw_devices] 0]
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quit
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""".format(bitstream=bitstream_file)
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_run_vivado(cmds)
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def flash(self, address, data_file):
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raise NotImplementedError
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_io = [
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("user_led", 0, Pins("AB8"), IOStandard("LVCMOS15")),
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("user_led", 1, Pins("AA8"), IOStandard("LVCMOS15")),
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("user_led", 2, Pins("AC9"), IOStandard("LVCMOS15")),
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("user_led", 3, Pins("AB9"), IOStandard("LVCMOS15")),
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("user_led", 4, Pins("AE26"), IOStandard("LVCMOS25")),
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("user_led", 5, Pins("G19"), IOStandard("LVCMOS25")),
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("user_led", 6, Pins("E18"), IOStandard("LVCMOS25")),
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("user_led", 7, Pins("F16"), IOStandard("LVCMOS25")),
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("cpu_reset", 0, Pins("AB7"), IOStandard("LVCMOS15")),
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("user_btn_c", 0, Pins("G12"), IOStandard("LVCMOS25")),
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("user_btn_n", 0, Pins("AA12"), IOStandard("LVCMOS15")),
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("user_btn_s", 0, Pins("AB12"), IOStandard("LVCMOS15")),
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("user_btn_w", 0, Pins("AC6"), IOStandard("LVCMOS15")),
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("user_btn_e", 0, Pins("AG5"), IOStandard("LVCMOS15")),
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("user_dip_btn", 0, Pins("Y29"), IOStandard("LVCMOS25")),
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("user_dip_btn", 1, Pins("W29"), IOStandard("LVCMOS25")),
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("user_dip_btn", 2, Pins("AA28"), IOStandard("LVCMOS25")),
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("user_dip_btn", 3, Pins("Y28"), IOStandard("LVCMOS25")),
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("clk200", 0,
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Subsignal("p", Pins("AD12"), IOStandard("LVDS")),
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Subsignal("n", Pins("AD11"), IOStandard("LVDS"))
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),
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("clk156", 0,
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Subsignal("p", Pins("K28"), IOStandard("LVDS_25")),
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Subsignal("n", Pins("K29"), IOStandard("LVDS_25"))
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),
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("serial", 0,
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Subsignal("cts", Pins("L27")),
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Subsignal("rts", Pins("K23")),
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Subsignal("tx", Pins("K24")),
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Subsignal("rx", Pins("M19")),
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IOStandard("LVCMOS25")
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),
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("sata_host", 0,
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Subsignal("refclk_p", Pins("C8")),
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Subsignal("refclk_n", Pins("C7")),
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Subsignal("txp", Pins("D2")),
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Subsignal("txn", Pins("D1")),
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Subsignal("rxp", Pins("E4")),
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Subsignal("rxn", Pins("E3")),
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),
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("sata_device", 0,
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Subsignal("refclk_p", Pins("G8")), # 125MHz SGMII
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Subsignal("refclk_n", Pins("G7")), # 125MHz SGMII
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Subsignal("txp", Pins("H2")), # SFP
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Subsignal("txn", Pins("H1")), # SFP
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Subsignal("rxp", Pins("G4")), # SFP
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Subsignal("rxn", Pins("G3")), # SFP
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),
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]
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def Platform(*args, toolchain="vivado", programmer="xc3sprog", **kwargs):
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if toolchain == "ise":
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xilinx_platform = XilinxISEPlatform
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elif toolchain == "vivado":
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xilinx_platform = XilinxVivadoPlatform
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else:
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raise ValueError
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class RealPlatform(xilinx_platform):
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bitgen_opt = "-g LCK_cycle:6 -g Binary:Yes -w -g ConfigRate:12 -g SPI_buswidth:4"
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def __init__(self, crg_factory=lambda p: CRG_DS(p, "clk156", "cpu_reset")):
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xilinx_platform.__init__(self, "xc7k325t-ffg900-2", _io, crg_factory)
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def create_programmer(self):
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if programmer == "xc3sprog":
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return XC3SProg("jtaghs1_fast", "bscan_spi_kc705.bit")
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elif programmer == "vivado":
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return VivadoProgrammer()
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else:
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raise ValueError
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def do_finalize(self, fragment):
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try:
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self.add_period_constraint(self.lookup_request("clk156").p, 6.4)
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except ConstraintError:
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pass
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try:
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self.add_period_constraint(self.lookup_request("clk200").p, 5.0)
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except ConstraintError:
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pass
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try:
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self.add_period_constraint(self.lookup_request("sata_host").refclk_p, 6.66)
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except ConstraintError:
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pass
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self.add_platform_command("""
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create_clock -name sys_clk -period 5 [get_nets sys_clk]
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create_clock -name sata_rx_clk -period 3.33 [get_nets sata_rx_clk]
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create_clock -name sata_tx_clk -period 3.33 [get_nets sata_tx_clk]
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set_false_path -from [get_clocks sys_clk] -to [get_clocks sata_rx_clk]
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set_false_path -from [get_clocks sys_clk] -to [get_clocks sata_tx_clk]
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set_false_path -from [get_clocks sata_rx_clk] -to [get_clocks sys_clk]
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set_false_path -from [get_clocks sata_tx_clk] -to [get_clocks sys_clk]
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set_property CFGBVS VCCO [current_design]
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set_property CONFIG_VOLTAGE 2.5 [current_design]
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""")
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return RealPlatform(*args, **kwargs)
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