183 lines
3.1 KiB
Python
183 lines
3.1 KiB
Python
from migen.fhdl.structure import *
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from migen.fhdl.module import *
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from migen.bus import csr
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from migen.genlib.fsm import FSM, NextState
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from miscope.com.uart2csr.uart import *
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WRITE_CMD = 0x01
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READ_CMD = 0x02
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CLOSE_CMD = 0x03
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class Uart2Csr(Module):
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def __init__(self, clk_freq, baud):
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# Uart interface
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self.rx = Signal()
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self.tx = Signal()
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# Csr interface
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self.csr = csr.Interface()
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###
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self.submodules.uart = UART(clk_freq, baud)
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uart = self.uart
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#
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# In/Out
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#
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self.comb +=[
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uart.rx.eq(self.rx),
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self.tx.eq(uart.tx)
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]
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cmd = Signal(8)
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cnt = Signal(3)
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sr = Signal(32)
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burst_cnt = Signal(8)
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addr = Signal(32)
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data = Signal(8)
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# FSM
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self.submodules.fsm = FSM(reset_state="IDLE")
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fsm = self.fsm
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#
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# Global
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#
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self.sync +=[
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If(fsm.ongoing("IDLE"), cnt.eq(0)
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).Elif(uart.rx_ev, cnt.eq(cnt + 1)),
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If(uart.rx_ev, sr.eq(Cat(uart.rx_dat, sr[0:24])))
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]
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# State done signals
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get_bl_done = Signal()
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get_addr_done = Signal()
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get_addr_done_d = Signal()
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get_data_done = Signal()
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send_data_done = Signal()
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#
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# Idle
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#
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fsm.act("IDLE",
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If(uart.rx_ev & ((uart.rx_dat == WRITE_CMD) | (uart.rx_dat == READ_CMD)),
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NextState("GET_BL")
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)
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)
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self.sync += If(fsm.ongoing("IDLE") & uart.rx_ev, cmd.eq(uart.rx_dat))
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#
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# Get burst length
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#
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fsm.act("GET_BL",
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If(get_bl_done,
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NextState("GET_ADDR")
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)
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)
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self.comb += get_bl_done.eq(uart.rx_ev & fsm.ongoing("GET_BL"))
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self.sync += If(get_bl_done, burst_cnt.eq(uart.rx_dat))
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#
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# Get address
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#
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fsm.act("GET_ADDR",
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If(get_addr_done & (cmd == WRITE_CMD),
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NextState("GET_DATA")
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).Elif(get_addr_done & (cmd == READ_CMD),
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NextState("READ_CSR0")
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)
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)
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self.comb += get_addr_done.eq(uart.rx_ev & (cnt == 4) & fsm.ongoing("GET_ADDR"))
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self.sync += get_addr_done_d.eq(get_addr_done)
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self.sync += [
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If(get_addr_done_d,
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addr.eq(sr)
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).Elif(fsm.leaving("WRITE_CSR") | send_data_done,
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addr.eq(addr + 1)
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)
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]
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#
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# Get data
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#
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fsm.act("GET_DATA",
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If(get_data_done,
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NextState("WRITE_CSR")
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)
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)
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self.comb += get_data_done.eq(uart.rx_ev & fsm.ongoing("GET_DATA"))
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self.sync += [
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If(get_data_done,
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burst_cnt.eq(burst_cnt-1),
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data.eq(uart.rx_dat)
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)
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]
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#
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# Write Csr
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#
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fsm.act("WRITE_CSR",
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If((burst_cnt==0),
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NextState("IDLE")
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).Else(NextState("GET_DATA"))
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)
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#
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# Read Csr0
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#
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fsm.act("READ_CSR0",
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NextState("READ_CSR1")
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)
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self.sync += If(fsm.entering("READ_CSR0"), burst_cnt.eq(burst_cnt-1))
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#
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# Read Csr1
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#
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fsm.act("READ_CSR1",
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NextState("SEND_DATA")
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)
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#
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# Send Data
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#
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fsm.act("SEND_DATA",
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If(send_data_done & (burst_cnt==0),
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NextState("IDLE")
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).Elif(send_data_done,
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NextState("READ_CSR0")
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)
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)
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self.comb += send_data_done.eq(fsm.ongoing("SEND_DATA") & uart.tx_ev)
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self.sync += [
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uart.tx_dat.eq(self.csr.dat_r),
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uart.tx_we.eq(fsm.entering("SEND_DATA")),
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]
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#
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# Csr access
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#
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self.comb += self.csr.adr.eq(addr)
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self.sync +=[
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self.csr.dat_w.eq(data),
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If(fsm.ongoing("WRITE_CSR"),
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self.csr.we.eq(1)
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).Else(
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self.csr.we.eq(0)
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)
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] |