225 lines
8.3 KiB
Python
225 lines
8.3 KiB
Python
from operator import itemgetter
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from math import ceil
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from migen.fhdl.std import *
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from migen.bank import csrgen
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from migen.bus import wishbone, csr, lasmibus, dfi
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from migen.bus import wishbone2lasmi, wishbone2csr
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from misoclib import uart, identifier, timer
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from misoclib.cpu import lm32, mor1kx
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from misoclib.sdram import lasmicon
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from misoclib.sdram import dfii
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from misoclib.sdram import memtest
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from misoclib.sdram.minicon import Minicon
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def mem_decoder(address, start=26, end=29):
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return lambda a: a[start:end] == ((address >> (start+2)) & (2**(end-start))-1)
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class GenSoC(Module):
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csr_map = {
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"crg": 0, # user
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"uart": 1, # provided by default
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"identifier": 2, # provided
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"timer0": 3, # provided
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"buttons": 4, # user
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"leds": 5, # user
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}
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interrupt_map = {
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"uart": 0,
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"timer0": 1,
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}
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mem_map = {
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"rom": 0x00000000, # (shadow @0x80000000)
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"sram": 0x10000000, # (shadow @0x90000000)
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"csr": 0x60000000, # (shadow @0xe0000000)
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}
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def __init__(self, platform, clk_freq, cpu_reset_address, sram_size=4096, l2_size=0, with_uart=True, cpu_type="lm32",
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csr_data_width=8, csr_address_width=14):
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self.clk_freq = clk_freq
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self.cpu_reset_address = cpu_reset_address
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self.sram_size = sram_size
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self.l2_size = l2_size
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self.cpu_type = cpu_type
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self.csr_data_width = csr_data_width
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self.csr_address_width = csr_address_width
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self.cpu_memory_regions = []
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self.cpu_csr_regions = [] # list of (name, origin, busword, csr_list/Memory)
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self._rom_registered = False
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# Wishbone
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if cpu_type == "lm32":
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self.submodules.cpu = lm32.LM32(platform, cpu_reset_address)
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elif cpu_type == "or1k":
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self.submodules.cpu = mor1kx.MOR1KX(platform, cpu_reset_address)
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else:
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raise ValueError("Unsupported CPU type: "+cpu_type)
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self.submodules.sram = wishbone.SRAM(sram_size)
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self.submodules.wishbone2csr = wishbone2csr.WB2CSR(bus_csr=csr.Interface(csr_data_width, csr_address_width))
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# rom 0x00000000 (shadow @0x80000000) from register_rom
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# SRAM/debug 0x10000000 (shadow @0x90000000) provided
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# CSR bridge 0x60000000 (shadow @0xe0000000) provided
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self._wb_masters = [self.cpu.ibus, self.cpu.dbus]
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self._wb_slaves = [
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(mem_decoder(self.mem_map["sram"]), self.sram.bus),
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(mem_decoder(self.mem_map["csr"]), self.wishbone2csr.wishbone)
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]
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self.add_cpu_memory_region("sram", self.mem_map["sram"], sram_size)
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# CSR
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if with_uart:
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self.submodules.uart = uart.UART(platform.request("serial"), clk_freq, baud=115200)
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platform_id = 0x554E if not hasattr(platform, "identifier") else platform.identifier
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self.submodules.identifier = identifier.Identifier(platform_id, int(clk_freq),
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log2_int(l2_size) if l2_size else 0)
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self.submodules.timer0 = timer.Timer()
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def register_rom(self, rom_wb_if, bios_size=0xa000):
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if self._rom_registered:
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raise FinalizeError
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self._rom_registered = True
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self.add_wb_slave(mem_decoder(self.mem_map["rom"]), rom_wb_if)
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self.add_cpu_memory_region("rom", self.cpu_reset_address, bios_size)
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def add_wb_master(self, wbm):
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if self.finalized:
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raise FinalizeError
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self._wb_masters.append(wbm)
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def add_wb_slave(self, address_decoder, interface):
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if self.finalized:
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raise FinalizeError
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self._wb_slaves.append((address_decoder, interface))
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def check_cpu_memory_region(self, name, origin):
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for n, o, l in self.cpu_memory_regions:
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if n == name or o == origin:
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raise ValueError("Memory region conflict between {} and {}".format(n, name))
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def add_cpu_memory_region(self, name, origin, length):
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self.check_cpu_memory_region(name, origin)
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self.cpu_memory_regions.append((name, origin, length))
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def check_cpu_csr_region(self, name, origin):
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for n, o, l, obj in self.cpu_csr_regions:
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if n == name or o == origin:
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raise ValueError("CSR region conflict between {} and {}".format(n, name))
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def add_cpu_csr_region(self, name, origin, busword, obj):
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self.check_cpu_csr_region(name, origin)
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self.cpu_csr_regions.append((name, origin, busword, obj))
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def do_finalize(self):
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if not self._rom_registered:
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raise FinalizeError("Need to call GenSoC.register_rom()")
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# Wishbone
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self.submodules.wishbonecon = wishbone.InterconnectShared(self._wb_masters,
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self._wb_slaves, register=True)
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# CSR
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self.submodules.csrbankarray = csrgen.BankArray(self,
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lambda name, memory: self.csr_map[name if memory is None else name + "_" + memory.name_override],
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data_width=self.csr_data_width, address_width=self.csr_address_width)
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self.submodules.csrcon = csr.Interconnect(self.wishbone2csr.csr, self.csrbankarray.get_buses())
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for name, csrs, mapaddr, rmap in self.csrbankarray.banks:
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self.add_cpu_csr_region(name, self.mem_map["csr"]+0x80000000+0x800*mapaddr, flen(rmap.bus.dat_w), csrs)
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for name, memory, mapaddr, mmap in self.csrbankarray.srams:
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self.add_cpu_csr_region(name, self.mem_map["csr"]+0x80000000+0x800*mapaddr, flen(rmap.bus.dat_w), memory)
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# Interrupts
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for k, v in sorted(self.interrupt_map.items(), key=itemgetter(1)):
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if hasattr(self, k):
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self.comb += self.cpu.interrupt[v].eq(getattr(self, k).ev.irq)
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def ns(self, t, margin=True):
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clk_period_ns = 1000000000/self.clk_freq
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if margin:
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t += clk_period_ns/2
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return ceil(t/clk_period_ns)
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def do_exit(self, vns):
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pass
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class IntegratedBIOS:
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def __init__(self, bios_size=0x8000):
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self.submodules.rom = wishbone.SRAM(bios_size, read_only=True)
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self.register_rom(self.rom.bus, bios_size)
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def init_bios_memory(self, data):
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self.rom.mem.init = data
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class SDRAMSoC(GenSoC):
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csr_map = {
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"dfii": 6,
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"lasmicon": 7,
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"memtest_w": 8,
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"memtest_r": 9
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}
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csr_map.update(GenSoC.csr_map)
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mem_map = {
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"sdram": 0x40000000, # (shadow @0xc0000000)
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}
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mem_map.update(GenSoC.mem_map)
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def __init__(self, platform, clk_freq, cpu_reset_address, with_memtest=False, sram_size=4096, l2_size=8192, with_uart=True, ramcon_type="lasmicon", **kwargs):
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GenSoC.__init__(self, platform, clk_freq, cpu_reset_address, sram_size, l2_size, with_uart, **kwargs)
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self.with_memtest = with_memtest
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self.ramcon_type = ramcon_type
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self._sdram_phy_registered = False
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def register_sdram_phy(self, phy_dfi, phy_settings, sdram_geom, sdram_timing):
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if self._sdram_phy_registered:
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raise FinalizeError
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self._sdram_phy_registered = True
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# DFI
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self.submodules.dfii = dfii.DFIInjector(sdram_geom.mux_a, sdram_geom.bank_a,
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phy_settings.dfi_d, phy_settings.nphases)
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self.submodules.dficon0 = dfi.Interconnect(self.dfii.master, phy_dfi)
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# LASMICON
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if self.ramcon_type == "lasmicon":
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self.submodules.lasmicon = lasmicon.LASMIcon(phy_settings, sdram_geom, sdram_timing)
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self.submodules.dficon1 = dfi.Interconnect(self.lasmicon.dfi, self.dfii.slave)
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self.submodules.lasmixbar = lasmibus.Crossbar([self.lasmicon.lasmic], self.lasmicon.nrowbits)
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if self.with_memtest:
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self.submodules.memtest_w = memtest.MemtestWriter(self.lasmixbar.get_master())
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self.submodules.memtest_r = memtest.MemtestReader(self.lasmixbar.get_master())
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# Wishbone bridge
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self.submodules.wishbone2lasmi = wishbone2lasmi.WB2LASMI(self.l2_size//4, self.lasmixbar.get_master())
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self.add_wb_slave(mem_decoder(self.mem_map["sdram"]), self.wishbone2lasmi.wishbone)
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self.add_cpu_memory_region("sdram", self.mem_map["sdram"],
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2**self.lasmicon.lasmic.aw*self.lasmicon.lasmic.dw*self.lasmicon.lasmic.nbanks//8)
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# MINICON
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elif self.ramcon_type == "minicon":
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self.submodules.minicon = sdramcon = Minicon(phy_settings, sdram_geom, sdram_timing)
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self.submodules.dficon1 = dfi.Interconnect(sdramcon.dfi, self.dfii.slave)
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sdram_width = flen(sdramcon.bus.dat_r)
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if (sdram_width == 32):
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self.add_wb_slave(mem_decoder(self.mem_map["sdram"]), sdramcon.bus)
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elif (sdram_width < 32):
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self.submodules.dc = wishbone.DownConverter(32, sdram_width)
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self.submodules.intercon = wishbone.InterconnectPointToPoint(self.dc.wishbone_o, sdramcon.bus)
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self.add_wb_slave(mem_decoder(self.mem_map["sdram"]), self.dc.wishbone_i)
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else:
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raise NotImplementedError("Unsupported SDRAM width of {} > 32".format(sdram_width))
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# Wishbone bridge
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self.add_cpu_memory_region("sdram", self.mem_map["sdram"],
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2**(sdram_geom.bank_a+sdram_geom.row_a+sdram_geom.col_a)*sdram_width//8)
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else:
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raise ValueError("Unsupported SDRAM controller type: {}".format(self.ramcon_type))
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def do_finalize(self):
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if not self._sdram_phy_registered:
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raise FinalizeError("Need to call SDRAMSoC.register_sdram_phy()")
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GenSoC.do_finalize(self)
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