83 lines
2.9 KiB
Python
83 lines
2.9 KiB
Python
# This file is Copyright (c) 2019 Florent Kermarrec <florent@enjoy-digital.fr>
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# License: BSD
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import unittest
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from migen import *
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from litex.soc.cores.spi import SPIMaster, SPISlave
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class TestSPI(unittest.TestCase):
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def test_spi_master_syntax(self):
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spi_master = SPIMaster(pads=None, data_width=32, sys_clk_freq=100e6, spi_clk_freq=5e6)
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self.assertEqual(hasattr(spi_master, "pads"), 1)
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def test_spi_master_xfer_loopback_32b_32b(self):
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def generator(dut):
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yield dut.loopback.eq(1)
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yield dut.mosi.eq(0xdeadbeef)
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yield dut.length.eq(32)
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yield dut.start.eq(1)
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yield
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yield dut.start.eq(0)
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yield
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while (yield dut.done) == 0:
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yield
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self.assertEqual((yield dut.miso), 0xdeadbeef)
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dut = SPIMaster(pads=None, data_width=32, sys_clk_freq=100e6, spi_clk_freq=5e6, with_csr=False)
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run_simulation(dut, generator(dut))
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def test_spi_master_xfer_loopback_32b_16b(self):
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def generator(dut):
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yield dut.loopback.eq(1)
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yield dut.mosi.eq(0xbeef)
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yield dut.length.eq(16)
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yield dut.start.eq(1)
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yield
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yield dut.start.eq(0)
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yield
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while (yield dut.done) == 0:
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yield
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self.assertEqual((yield dut.miso), 0xbeef)
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dut = SPIMaster(pads=None, data_width=32, sys_clk_freq=100e6, spi_clk_freq=5e6, with_csr=False, mode="aligned")
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run_simulation(dut, generator(dut))
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def test_spi_slave_syntax(self):
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spi_slave = SPISlave(pads=None, data_width=32)
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self.assertEqual(hasattr(spi_slave, "pads"), 1)
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def test_spi_slave_xfer(self):
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class DUT(Module):
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def __init__(self):
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pads = Record([("clk", 1), ("cs_n", 1), ("mosi", 1), ("miso", 1)])
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self.submodules.master = SPIMaster(pads, data_width=32,
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sys_clk_freq=100e6, spi_clk_freq=5e6,
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with_csr=False)
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self.submodules.slave = SPISlave(pads, data_width=32)
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def master_generator(dut):
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yield dut.master.mosi.eq(0xdeadbeef)
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yield dut.master.length.eq(32)
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yield dut.master.start.eq(1)
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yield
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yield dut.master.start.eq(0)
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yield
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while (yield dut.master.done) == 0:
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yield
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self.assertEqual((yield dut.master.miso), 0x12345678)
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def slave_generator(dut):
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yield dut.slave.miso.eq(0x12345678)
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while (yield dut.slave.start) == 0:
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yield
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while (yield dut.slave.done) == 0:
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yield
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self.assertEqual((yield dut.slave.mosi), 0xdeadbeef)
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self.assertEqual((yield dut.slave.length), 32)
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dut = DUT()
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run_simulation(dut, [master_generator(dut), slave_generator(dut)])
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