Florent Kermarrec 9adf3f02f2 fhdl/verilog: add simulation parameter to avoid simulation tricks in synthetizable code ... it's generally better to have identical code between simulations and synthesis, but here tricks inserted for simulation are clearly expected to be simplified by synthesis tools, so it's better not inserting them.		2015-03-17 00:40:26 +01:00
..
altera	mibuild/altera: use new Toolchain/Platform architecture	2015-03-16 21:07:55 +01:00
lattice	mibuild/xilinx/common: add LatticeDDROutput	2015-03-16 22:57:18 +01:00
platforms	mibuild/platforms: add ethernet to versa	2015-03-16 22:24:10 +01:00
sim	mibuild/sim: clean up (thanks sb)	2015-03-10 16:41:52 +01:00
xilinx	mibuild/xilinx/common: add XilinxDDROutput	2015-03-16 22:53:05 +01:00
__init__.py	merge Mibuild into Migen	2013-11-23 10:45:15 +01:00
generic_platform.py	fhdl/verilog: add simulation parameter to avoid simulation tricks in synthetizable code	2015-03-17 00:40:26 +01:00
generic_programmer.py	mibuild: better file organization (create directory for each vendor and move programmers in it)	2015-02-26 12:25:59 +01:00
tools.py	remove trailing whitespaces	2014-10-17 17:08:46 +08:00