53 lines
1.5 KiB
Python
53 lines
1.5 KiB
Python
import random
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from migen.fhdl.std import *
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from migen.genlib.record import *
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from migen.sim.generic import run_simulation
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from lib.sata.std import *
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from lib.sata.link import SATALinkLayer
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from lib.sata.transport import SATATransportLayer
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from lib.sata.test.bfm import *
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from lib.sata.test.common import *
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class TB(Module):
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def __init__(self):
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self.submodules.bfm = BFM(phy_debug=False,
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link_random_level=0, transport_debug=True, transport_loopback=True)
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self.submodules.link = SATALinkLayer(self.bfm.phy)
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self.submodules.transport = SATATransportLayer(self.link)
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def gen_simulation(self, selfp):
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for i in range(100):
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yield
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selfp.transport.tx.cmd.stb = 1
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selfp.transport.tx.cmd.type = fis_types["REG_H2D"]
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selfp.transport.tx.cmd.lba = 0x0123456789
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yield
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while selfp.transport.tx.cmd.ack == 0:
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yield
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selfp.transport.tx.cmd.stb = 1
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selfp.transport.tx.cmd.type = fis_types["DMA_SETUP"]
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selfp.transport.tx.cmd.dma_buffer_id = 0x0123456789ABCDEF
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yield
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while selfp.transport.tx.cmd.ack == 0:
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yield
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selfp.transport.tx.cmd.stb = 1
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selfp.transport.tx.cmd.type = fis_types["DATA"]
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yield
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for i in range(32):
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selfp.transport.tx.data.stb = 1
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#selfp.transport.tx.data.sop = (i==0)
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selfp.transport.tx.data.eop = (i==31)
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selfp.transport.tx.data.d = i
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if selfp.transport.tx.data.ack == 1:
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yield
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else:
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while selfp.transport.tx.data.ack == 0:
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yield
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selfp.transport.tx.cmd.stb = 0
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if __name__ == "__main__":
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run_simulation(TB(), ncycles=512, vcd_name="my.vcd", keep_files=True)
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