44 lines
832 B
Verilog
44 lines
832 B
Verilog
`timescale 1ns/1ps
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module top_tb();
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reg refclk_p;
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wire refclk_n;
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initial refclk_p = 1'b1;
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always #3.33 refclk_p = ~refclk_p;
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assign refclk_n = ~refclk_p;
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reg clk200_p;
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wire clk200_n;
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initial clk200_p = 1'b1;
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always #2.5 clk200_p = ~clk200_p;
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assign clk200_n = ~clk200_p;
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wire sata_txp;
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wire sata_txn;
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wire sata_rxp;
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wire sata_rxn;
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top dut(
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.serial_cts(1'b0),
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.serial_rts(1'b0),
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.serial_tx(),
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.serial_rx(1'b0),
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.clk200_p(clk200_p),
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.clk200_n(clk200_n),
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.sata_host_refclk_p(refclk_p),
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.sata_host_refclk_n(refclk_n),
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.sata_host_txp(sata_txp),
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.sata_host_txn(sata_txn),
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.sata_host_rxp(sata_rxp),
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.sata_host_rxn(sata_rxn),
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.sata_device_refclk_p(refclk_p),
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.sata_device_refclk_n(refclk_n),
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.sata_device_txp(sata_rxp),
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.sata_device_txn(sata_rxn),
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.sata_device_rxp(sata_txp),
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.sata_device_rxn(sata_txn)
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);
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endmodule
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