71 lines
2.1 KiB
Python
71 lines
2.1 KiB
Python
from migen import *
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from migen.genlib.misc import timeline
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from migen.genlib.fsm import FSM
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from misoc.mem.sdram.core.lasmicon.multiplexer import *
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class Refresher(Module):
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def __init__(self, a, ba, tRP, tREFI, tRFC, enabled=True):
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self.req = Signal()
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self.ack = Signal() # 1st command 1 cycle after assertion of ack
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self.cmd = CommandRequest(a, ba)
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###
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if enabled:
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# Refresh sequence generator:
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# PRECHARGE ALL --(tRP)--> AUTO REFRESH --(tRFC)--> done
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seq_start = Signal()
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seq_done = Signal()
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self.sync += [
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self.cmd.a.eq(2**10),
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self.cmd.ba.eq(0),
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self.cmd.cas_n.eq(1),
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self.cmd.ras_n.eq(1),
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self.cmd.we_n.eq(1),
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seq_done.eq(0)
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]
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self.sync += timeline(seq_start, [
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(1, [
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self.cmd.ras_n.eq(0),
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self.cmd.we_n.eq(0)
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]),
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(1+tRP, [
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self.cmd.cas_n.eq(0),
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self.cmd.ras_n.eq(0)
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]),
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(1+tRP+tRFC, [
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seq_done.eq(1)
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])
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])
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# Periodic refresh counter
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counter = Signal(max=tREFI)
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start = Signal()
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self.sync += [
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start.eq(0),
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If(counter == 0,
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start.eq(1),
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counter.eq(tREFI - 1)
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).Else(
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counter.eq(counter - 1)
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)
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]
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# Control FSM
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fsm = FSM()
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self.submodules += fsm
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fsm.act("IDLE", If(start, NextState("WAIT_GRANT")))
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fsm.act("WAIT_GRANT",
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self.req.eq(1),
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If(self.ack,
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seq_start.eq(1),
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NextState("WAIT_SEQ")
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)
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)
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fsm.act("WAIT_SEQ",
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self.req.eq(1),
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If(seq_done, NextState("IDLE"))
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)
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