litex/litex/gen/fhdl
2022-05-09 17:53:27 +02:00
..
__init__.py litex/gen: reintegrate migen with modifications to be able to simulate with vpi until all missing features of the new simulator are implemented 2015-11-13 14:44:16 +01:00
memory.py fhdl/memory/namer: Improve readability. 2022-05-09 10:22:48 +02:00
namer.py gen/fhdl/namer: Minor cleanup to ease readability. 2022-05-09 17:53:27 +02:00
verilog.py fhdl/memory: Prefix memory files with build name. 2022-05-06 20:21:30 +02:00