litex/litex
Florent Kermarrec 9c6f76f18c bios/sdram: mode sdhw() 2018-09-13 06:33:54 +02:00
..
boards targets: self.pll_sys --> pll_sys 2018-09-13 05:31:35 +02:00
build lattice/programmer: Use --program-image option with tinyprog if address is given. 2018-09-07 04:05:49 -04:00
gen build: use our own fhdl/verilog code (needed to avoid combinatorial loop in simulation) 2018-05-01 12:02:54 +02:00
soc bios/sdram: mode sdhw() 2018-09-13 06:33:54 +02:00
__init__.py litex: reorganize things, first work working version 2015-11-07 17:48:55 +01:00