litex/misoclib
2015-03-03 09:02:53 +01:00
..
com sdram: create frontend dir and move dma_lasmi/memtest/wishbone2lasmi to it 2015-03-02 08:36:39 +01:00
cpu litescope: create example design derived from SoC that can be used on all targets 2015-02-28 22:19:24 +01:00
mem lasmicon: better management of optional bandwidth module (automatically inserted by -Ot with_memtest True) 2015-03-03 09:02:53 +01:00
others
soc lasmicon: better management of optional bandwidth module (automatically inserted by -Ot with_memtest True) 2015-03-03 09:02:53 +01:00
tools uart: use data instead of d on endpoint's layouts (coherency with others cores) 2015-03-01 16:56:48 +01:00
video sdram: create frontend dir and move dma_lasmi/memtest/wishbone2lasmi to it 2015-03-02 08:36:39 +01:00
__init__.py