122 lines
3.1 KiB
Python
122 lines
3.1 KiB
Python
from migen.fhdl.std import *
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from migen.flow.actor import *
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from migen.bank.description import CSRStorage
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from migen.actorlib import spi
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_hbits = 12
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_vbits = 12
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bpp = 32
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bpc = 10
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pixel_layout_s = [
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("pad", bpp-3*bpc),
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("r", bpc),
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("g", bpc),
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("b", bpc)
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]
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def pixel_layout(pack_factor):
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return [("p"+str(i), pixel_layout_s) for i in range(pack_factor)]
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bpc_phy = 8
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phy_layout_s = [
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("r", bpc_phy),
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("g", bpc_phy),
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("b", bpc_phy)
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]
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def phy_layout(pack_factor):
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r = [("hsync", 1), ("vsync", 1), ("de", 1)]
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for i in range(pack_factor):
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r.append(("p"+str(i), phy_layout_s))
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return r
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class FrameInitiator(spi.SingleGenerator):
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def __init__(self, pack_factor):
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h_alignment_bits = log2_int(pack_factor)
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hbits_dyn = _hbits - h_alignment_bits
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layout = [
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("hres", hbits_dyn, 640, h_alignment_bits),
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("hsync_start", hbits_dyn, 656, h_alignment_bits),
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("hsync_end", hbits_dyn, 752, h_alignment_bits),
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("hscan", hbits_dyn, 800, h_alignment_bits),
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("vres", _vbits, 480),
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("vsync_start", _vbits, 492),
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("vsync_end", _vbits, 494),
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("vscan", _vbits, 525)
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]
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spi.SingleGenerator.__init__(self, layout, spi.MODE_EXTERNAL)
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class VTG(Module):
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def __init__(self, pack_factor):
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hbits_dyn = _hbits - log2_int(pack_factor)
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self.enable = Signal()
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self.timing = Sink([
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("hres", hbits_dyn),
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("hsync_start", hbits_dyn),
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("hsync_end", hbits_dyn),
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("hscan", hbits_dyn),
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("vres", _vbits),
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("vsync_start", _vbits),
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("vsync_end", _vbits),
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("vscan", _vbits)])
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self.pixels = Sink(pixel_layout(pack_factor))
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self.phy = Source(phy_layout(pack_factor))
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self.busy = Signal()
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###
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hactive = Signal()
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vactive = Signal()
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active = Signal()
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generate_en = Signal()
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hcounter = Signal(hbits_dyn)
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vcounter = Signal(_vbits)
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skip = bpc - bpc_phy
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self.comb += [
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active.eq(hactive & vactive),
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If(active,
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[getattr(getattr(self.phy.payload, p), c).eq(getattr(getattr(self.pixels.payload, p), c)[skip:])
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for p in ["p"+str(i) for i in range(pack_factor)] for c in ["r", "g", "b"]],
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self.phy.payload.de.eq(1)
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),
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generate_en.eq(self.timing.stb & (~active | self.pixels.stb)),
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self.pixels.ack.eq(~self.enable | (self.phy.ack & active)),
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self.phy.stb.eq(generate_en),
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self.busy.eq(generate_en)
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]
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tp = self.timing.payload
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self.sync += [
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If(self.enable,
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self.timing.ack.eq(0),
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If(generate_en & self.phy.ack,
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hcounter.eq(hcounter + 1),
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If(hcounter == 0, hactive.eq(1)),
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If(hcounter == tp.hres, hactive.eq(0)),
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If(hcounter == tp.hsync_start, self.phy.payload.hsync.eq(1)),
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If(hcounter == tp.hsync_end, self.phy.payload.hsync.eq(0)),
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If(hcounter == tp.hscan,
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hcounter.eq(0),
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If(vcounter == tp.vscan,
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vcounter.eq(0),
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self.timing.ack.eq(1)
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).Else(
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vcounter.eq(vcounter + 1)
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)
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),
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If(vcounter == 0, vactive.eq(1)),
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If(vcounter == tp.vres, vactive.eq(0)),
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If(vcounter == tp.vsync_start, self.phy.payload.vsync.eq(1)),
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If(vcounter == tp.vsync_end, self.phy.payload.vsync.eq(0))
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)
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).Else(
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self.timing.ack.eq(1),
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hcounter.eq(0),
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vcounter.eq(0)
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)
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]
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