135 lines
4.6 KiB
Python
135 lines
4.6 KiB
Python
from fractions import Fraction
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from migen.fhdl.std import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from misoclib.mem import sdram
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from misoclib.mem.sdram.phy import s6ddrphy
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from misoclib.mem.flash import spiflash
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from misoclib.soc.sdram import SDRAMSoC
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class _CRG(Module):
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def __init__(self, platform, clk_freq):
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_sdram_half = ClockDomain()
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self.clock_domains.cd_sdram_full_wr = ClockDomain()
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self.clock_domains.cd_sdram_full_rd = ClockDomain()
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self.clk4x_wr_strb = Signal()
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self.clk4x_rd_strb = Signal()
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f0 = 50*1000*1000
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clk50 = platform.request("clk50")
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clk50a = Signal()
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self.specials += Instance("IBUFG", i_I=clk50, o_O=clk50a)
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clk50b = Signal()
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self.specials += Instance("BUFIO2", p_DIVIDE=1,
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p_DIVIDE_BYPASS="TRUE", p_I_INVERT="FALSE",
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i_I=clk50a, o_DIVCLK=clk50b)
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f = Fraction(int(clk_freq), int(f0))
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n, m = f.denominator, f.numerator
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assert f0/n*m == clk_freq
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p = 8
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pll_lckd = Signal()
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pll_fb = Signal()
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pll = Signal(6)
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self.specials.pll = Instance("PLL_ADV", p_SIM_DEVICE="SPARTAN6",
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p_BANDWIDTH="OPTIMIZED", p_COMPENSATION="INTERNAL",
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p_REF_JITTER=.01, p_CLK_FEEDBACK="CLKFBOUT",
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i_DADDR=0, i_DCLK=0, i_DEN=0, i_DI=0, i_DWE=0, i_RST=0, i_REL=0,
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p_DIVCLK_DIVIDE=1, p_CLKFBOUT_MULT=m*p//n, p_CLKFBOUT_PHASE=0.,
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i_CLKIN1=clk50b, i_CLKIN2=0, i_CLKINSEL=1,
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p_CLKIN1_PERIOD=1/f0, p_CLKIN2_PERIOD=0.,
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i_CLKFBIN=pll_fb, o_CLKFBOUT=pll_fb, o_LOCKED=pll_lckd,
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o_CLKOUT0=pll[0], p_CLKOUT0_DUTY_CYCLE=.5,
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o_CLKOUT1=pll[1], p_CLKOUT1_DUTY_CYCLE=.5,
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o_CLKOUT2=pll[2], p_CLKOUT2_DUTY_CYCLE=.5,
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o_CLKOUT3=pll[3], p_CLKOUT3_DUTY_CYCLE=.5,
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o_CLKOUT4=pll[4], p_CLKOUT4_DUTY_CYCLE=.5,
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o_CLKOUT5=pll[5], p_CLKOUT5_DUTY_CYCLE=.5,
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p_CLKOUT0_PHASE=0., p_CLKOUT0_DIVIDE=p//4, # sdram wr rd
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p_CLKOUT1_PHASE=0., p_CLKOUT1_DIVIDE=p//8,
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p_CLKOUT2_PHASE=270., p_CLKOUT2_DIVIDE=p//2, # sdram dqs adr ctrl
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p_CLKOUT3_PHASE=250., p_CLKOUT3_DIVIDE=p//2, # off-chip ddr
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p_CLKOUT4_PHASE=0., p_CLKOUT4_DIVIDE=p//1,
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p_CLKOUT5_PHASE=0., p_CLKOUT5_DIVIDE=p//1, # sys
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)
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self.specials += Instance("BUFG", i_I=pll[5], o_O=self.cd_sys.clk)
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self.specials += AsyncResetSynchronizer(self.cd_sys, ~pll_lckd)
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self.specials += Instance("BUFG", i_I=pll[2], o_O=self.cd_sdram_half.clk)
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self.specials += Instance("BUFPLL", p_DIVIDE=4,
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i_PLLIN=pll[0], i_GCLK=self.cd_sys.clk,
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i_LOCKED=pll_lckd, o_IOCLK=self.cd_sdram_full_wr.clk,
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o_SERDESSTROBE=self.clk4x_wr_strb)
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self.comb += [
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self.cd_sdram_full_rd.clk.eq(self.cd_sdram_full_wr.clk),
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self.clk4x_rd_strb.eq(self.clk4x_wr_strb),
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]
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clk_sdram_half_shifted = Signal()
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self.specials += Instance("BUFG", i_I=pll[3], o_O=clk_sdram_half_shifted)
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clk = platform.request("sdram_clock")
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self.specials += Instance("ODDR2", p_DDR_ALIGNMENT="NONE",
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p_INIT=0, p_SRTYPE="SYNC",
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i_D0=1, i_D1=0, i_S=0, i_R=0, i_CE=1,
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i_C0=clk_sdram_half_shifted, i_C1=~clk_sdram_half_shifted,
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o_Q=clk.p)
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self.specials += Instance("ODDR2", p_DDR_ALIGNMENT="NONE",
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p_INIT=0, p_SRTYPE="SYNC",
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i_D0=0, i_D1=1, i_S=0, i_R=0, i_CE=1,
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i_C0=clk_sdram_half_shifted, i_C1=~clk_sdram_half_shifted,
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o_Q=clk.n)
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class BaseSoC(SDRAMSoC):
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default_platform = "pipistrello"
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csr_map = {
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"spiflash": 16,
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}
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csr_map.update(SDRAMSoC.csr_map)
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def __init__(self, platform, **kwargs):
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clk_freq = 75*1000*1000
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if not kwargs.get("with_rom"):
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kwargs["rom_size"] = 0x1000000 # 128 Mb
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SDRAMSoC.__init__(self, platform, clk_freq,
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cpu_reset_address=0x170000, **kwargs) # 1.5 MB
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self.submodules.crg = _CRG(platform, clk_freq)
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if not self.with_main_ram:
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sdram_geom = sdram.GeomSettings(
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bank_a=2,
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row_a=13,
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col_a=10
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)
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sdram_timing = sdram.TimingSettings(
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tRP=self.ns(15),
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tRCD=self.ns(15),
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tWR=self.ns(15),
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tWTR=2,
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tREFI=self.ns(64*1000*1000/8192, False),
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tRFC=self.ns(72),
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req_queue_size=8,
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read_time=32,
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write_time=16
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)
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self.submodules.ddrphy = s6ddrphy.S6DDRPHY(platform.request("sdram"),
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"LPDDR", rd_bitslip=1, wr_bitslip=3, dqs_ddr_alignment="C1")
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self.comb += [
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self.ddrphy.clk4x_wr_strb.eq(self.crg.clk4x_wr_strb),
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self.ddrphy.clk4x_rd_strb.eq(self.crg.clk4x_rd_strb),
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]
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platform.add_platform_command("""
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PIN "BUFG.O" CLOCK_DEDICATED_ROUTE = FALSE;
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""")
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self.register_sdram_phy(self.ddrphy, sdram_geom, sdram_timing)
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self.submodules.spiflash = spiflash.SpiFlash(platform.request("spiflash4x"), dummy=11, div=2)
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self.flash_boot_address = 0x180000
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# If not in ROM, BIOS is in SPI flash
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if not self.with_rom:
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self.register_rom(self.spiflash.bus)
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default_subtarget = BaseSoC
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