99 lines
2.9 KiB
Python
99 lines
2.9 KiB
Python
import os
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from distutils.version import StrictVersion
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from migen.fhdl.std import *
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from migen.fhdl.specials import SynthesisDirective
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from migen.genlib.cdc import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from mibuild.generic_platform import GenericPlatform
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from mibuild import tools
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def settings(path, ver=None, sub=None):
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vers = list(tools.versions(path))
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if ver is None:
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ver = max(vers)
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else:
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ver = StrictVersion(ver)
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assert ver in vers
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full = os.path.join(path, str(ver))
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if sub:
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full = os.path.join(full, sub)
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search = [64, 32]
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if tools.arch_bits() == 32:
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search.reverse()
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for b in search:
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settings = os.path.join(full, "settings{0}.sh".format(b))
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if os.path.exists(settings):
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return settings
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raise ValueError("no settings file found")
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class CRG_DS(Module):
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def __init__(self, platform, clk_name, rst_name, rst_invert=False):
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reset_less = rst_name is None
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self.clock_domains.cd_sys = ClockDomain(reset_less=reset_less)
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self._clk = platform.request(clk_name)
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self.specials += Instance("IBUFGDS",
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Instance.Input("I", self._clk.p),
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Instance.Input("IB", self._clk.n),
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Instance.Output("O", self.cd_sys.clk)
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)
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if not reset_less:
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if rst_invert:
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self.comb += self.cd_sys.rst.eq(~platform.request(rst_name))
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else:
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self.comb += self.cd_sys.rst.eq(platform.request(rst_name))
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class XilinxNoRetimingImpl(Module):
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def __init__(self, reg):
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self.specials += SynthesisDirective("attribute register_balancing of {r} is no", r=reg)
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class XilinxNoRetiming:
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@staticmethod
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def lower(dr):
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return XilinxNoRetimingImpl(dr.reg)
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class XilinxMultiRegImpl(MultiRegImpl):
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def __init__(self, *args, **kwargs):
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MultiRegImpl.__init__(self, *args, **kwargs)
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self.specials += [SynthesisDirective("attribute shreg_extract of {r} is no", r=r)
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for r in self.regs]
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class XilinxMultiReg:
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@staticmethod
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def lower(dr):
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return XilinxMultiRegImpl(dr.i, dr.o, dr.odomain, dr.n)
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class XilinxAsyncResetSynchronizerImpl(Module):
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def __init__(self, cd, async_reset):
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rst1 = Signal()
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self.specials += [
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Instance("FDPE", p_INIT=1, i_D=0, i_PRE=async_reset,
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i_CE=1, i_C=cd.clk, o_Q=rst1),
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Instance("FDPE", p_INIT=1, i_D=rst1, i_PRE=async_reset,
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i_CE=1, i_C=cd.clk, o_Q=cd.rst)
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]
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class XilinxAsyncResetSynchronizer:
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@staticmethod
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def lower(dr):
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return XilinxAsyncResetSynchronizerImpl(dr.cd, dr.async_reset)
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class XilinxGenericPlatform(GenericPlatform):
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bitstream_ext = ".bit"
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def get_verilog(self, *args, special_overrides=dict(), **kwargs):
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so = {
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NoRetiming: XilinxNoRetiming,
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MultiReg: XilinxMultiReg,
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AsyncResetSynchronizer: XilinxAsyncResetSynchronizer
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}
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so.update(special_overrides)
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return GenericPlatform.get_verilog(self, *args, special_overrides=so, **kwargs)
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def get_edif(self, fragment, **kwargs):
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return GenericPlatform.get_edif(self, fragment, "UNISIMS", "Xilinx", self.device, **kwargs)
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