litex/mibuild/xilinx_ise.py

import os, subprocess, sys

from migen.fhdl.std import *
from migen.fhdl.structure import _Fragment

from mibuild.generic_platform import *
from mibuild import tools, xilinx_common

def _format_constraint(c):
	if isinstance(c, Pins):
		return "LOC=" + c.identifiers[0]
	elif isinstance(c, IOStandard):
		return "IOSTANDARD=" + c.name
	elif isinstance(c, Drive):
		return "DRIVE=" + str(c.strength)
	elif isinstance(c, Misc):
		return c.misc

def _format_ucf(signame, pin, others, resname):
	fmt_c = []
	for c in [Pins(pin)] + others:
		fc = _format_constraint(c)
		if fc is not None:
			fmt_c.append(fc)
	fmt_r = resname[0] + ":" + str(resname[1])
	if resname[2] is not None:
		fmt_r += "." + resname[2]
	return "NET \"" + signame + "\" " + " | ".join(fmt_c) + "; # " + fmt_r + "\n"

def _build_ucf(named_sc, named_pc):
	r = ""
	for sig, pins, others, resname in named_sc:
		if len(pins) > 1:
			for i, p in enumerate(pins):
				r += _format_ucf(sig + "(" + str(i) + ")", p, others, resname)
		else:
			r += _format_ucf(sig, pins[0], others, resname)
	if named_pc:
		r += "\n" + "\n\n".join(named_pc)
	return r

def _build_xst_files(device, sources, vincpaths, build_name, xst_opt):
	prj_contents = ""
	for filename, language in sources:
		prj_contents += language + " work " + filename + "\n"
	tools.write_to_file(build_name + ".prj", prj_contents)

	xst_contents = """run
-ifn {build_name}.prj
-top top
{xst_opt}
-ofn {build_name}.ngc
-p {device}
""".format(build_name=build_name, xst_opt=xst_opt, device=device)
	for path in vincpaths:
		xst_contents += "-vlgincdir " + path + "\n"
	tools.write_to_file(build_name + ".xst", xst_contents)

def _run_yosys(device, sources, vincpaths, build_name):
	ys_contents = ""
	incflags = ""
	for path in vincpaths:
		incflags += " -I" + path
	for filename, language in sources:
		ys_contents += "read_{}{} {}\n".format(language, incflags, filename)

	if device[:2] == "xc":
		archcode = device[2:4]
	else:
		archcode = device[0:2]
	arch = {
		"6s": "spartan6",
		"7a": "artix7",
		"7k": "kintex7",
		"7v": "virtex7",
		"7z": "zynq7000"
	}[archcode]

	ys_contents += """hierarchy -check -top top
proc; memory; opt; fsm; opt
synth_xilinx -arch {arch} -top top -edif {build_name}.edif""".format(arch=arch, build_name=build_name)

	ys_name = build_name + ".ys"
	tools.write_to_file(ys_name, ys_contents)
	r = subprocess.call(["yosys", ys_name])
	if r != 0:
		raise OSError("Subprocess failed")

def _run_ise(build_name, ise_path, source, mode, ngdbuild_opt,
		bitgen_opt, ise_commands, map_opt, par_opt, ver=None):
	if sys.platform == "win32" or sys.platform == "cygwin":
		source = False
	build_script_contents = "# Autogenerated by mibuild\nset -e\n"
	if source:
		settings = xilinx_common.settings(ise_path, ver, "ISE_DS")
		build_script_contents += "source " + settings + "\n"
	if mode == "edif":
		ext = "edif"
	else:
		ext = "ngc"
		build_script_contents += """
xst -ifn {build_name}.xst
"""

	build_script_contents += """
ngdbuild {ngdbuild_opt} -uc {build_name}.ucf {build_name}.{ext} {build_name}.ngd
map {map_opt} -o {build_name}_map.ncd {build_name}.ngd {build_name}.pcf
par {par_opt} {build_name}_map.ncd {build_name}.ncd {build_name}.pcf
bitgen {bitgen_opt} {build_name}.ncd {build_name}.bit
"""
	build_script_contents = build_script_contents.format(build_name=build_name,
			ngdbuild_opt=ngdbuild_opt, bitgen_opt=bitgen_opt, ext=ext,
			par_opt=par_opt, map_opt=map_opt)
	build_script_contents += ise_commands.format(build_name=build_name)
	build_script_file = "build_" + build_name + ".sh"
	tools.write_to_file(build_script_file, build_script_contents, force_unix=True)

	r = subprocess.call(["bash", build_script_file])
	if r != 0:
		raise OSError("Subprocess failed")

class XilinxISEPlatform(xilinx_common.XilinxGenericPlatform):
	xst_opt = """-ifmt MIXED
-opt_mode SPEED
-register_balancing yes"""
	map_opt = "-ol high -w"
	par_opt = "-ol high -w"
	ngdbuild_opt = ""
	bitgen_opt = "-g LCK_cycle:6 -g Binary:Yes -w"
	ise_commands = ""

	def build(self, fragment, build_dir="build", build_name="top",
			ise_path="/opt/Xilinx", source=True, run=True, mode="xst"):
		tools.mkdir_noerror(build_dir)
		os.chdir(build_dir)

		if not isinstance(fragment, _Fragment):
			fragment = fragment.get_fragment()
		self.finalize(fragment)

		ngdbuild_opt = self.ngdbuild_opt

		if mode == "xst" or mode == "yosys":
			v_src, named_sc, named_pc = self.get_verilog(fragment)
			v_file = build_name + ".v"
			tools.write_to_file(v_file, v_src)
			sources = self.sources + [(v_file, "verilog")]
			if mode == "xst":
				_build_xst_files(self.device, sources, self.verilog_include_paths, build_name, self.xst_opt)
				isemode = "xst"
			else:
				_run_yosys(self.device, sources, self.verilog_include_paths, build_name)
				isemode = "edif"
				ngdbuild_opt += "-p " + self.device

		if mode == "mist":
			from mist import synthesize
			synthesize(fragment, self.constraint_manager.get_io_signals())

		if mode == "edif" or mode == "mist":
			e_src, named_sc, named_pc = self.get_edif(fragment)
			e_file = build_name + ".edif"
			tools.write_to_file(e_file, e_src)
			isemode = "edif"

		tools.write_to_file(build_name + ".ucf", _build_ucf(named_sc, named_pc))
		if run:
			_run_ise(build_name, ise_path, source, isemode,
					ngdbuild_opt, self.bitgen_opt, self.ise_commands,
					self.map_opt, self.par_opt)

		os.chdir("..")

	def add_period_constraint(self, clk, period):
		self.add_platform_command("""NET "{clk}" TNM_NET = "GRP{clk}";
TIMESPEC "TS{clk}" = PERIOD "GRP{clk}" """+str(period)+""" ns HIGH 50%;""", clk=clk)