mirror of
https://github.com/enjoy-digital/litex.git
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2886fe1701
* Add bios test mode for CI This enables to test the booting of each CPU configurations with the bios in Verilator simulation.
49 lines
1.4 KiB
YAML
49 lines
1.4 KiB
YAML
name: ci
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on: [push, pull_request]
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jobs:
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regression-test:
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runs-on: ubuntu-18.04
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steps:
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# Checkout Repository
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- name: Checkout
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uses: actions/checkout@v2
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# Install Tools
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- name: Install Tools
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run: |
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sudo apt-get install wget build-essential python3
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sudo apt-get install verilator libevent-dev libjson-c-dev
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pip3 install setuptools
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pip3 install requests
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pip3 install meson
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pip3 install ninja
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pip3 install nmigen-yosys
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pip3 install pexpect
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# Install (n)Migen / LiteX / Cores
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- name: Install LiteX
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run: |
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wget https://raw.githubusercontent.com/enjoy-digital/litex/master/litex_setup.py
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python3 litex_setup.py init install --user
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# Install RISC-V GCC
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- name: Install RISC-V GCC
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run: |
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wget https://raw.githubusercontent.com/enjoy-digital/litex/master/litex_setup.py
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python3 litex_setup.py gcc
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ls $PWD/../riscv64-*/bin/
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export PATH=$PATH:$(echo $PWD/../riscv64-*/bin/)
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riscv64-unknown-elf-gcc --version
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# Install Project
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- name: Install Project
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run: python3 setup.py develop --user
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# Test
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- name: Run Tests
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run: |
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export GITHUB_ACTIONS=1
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export PATH=$PATH:$(echo $PWD/../riscv64-*/bin/)
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python3 setup.py test
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