145 lines
5.2 KiB
Plaintext
145 lines
5.2 KiB
Plaintext
__ _ __ _ __
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/ / (_) /____ | |/_/
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/ /__/ / __/ -_)> <
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/____/_/\__/\__/_/|_|
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Build your hardware, easily!
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Copyright 2012-2019 / EnjoyDigital
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[> Intro
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--------
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LiteX is a MiSoC-based SoC builder using Migen as Python DSL that can be used
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to create SoCs and full FPGA designs.
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LiteX provides specific building/debugging tools for high level of abstraction
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and compatibily with the LiteX core ecosystem.
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Think of Migen as a toolbox to create FPGA designs in Python and LiteX as a
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toolbox to create/develop/debug FPGA SoCs in Python.
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Typical LiteX design flow:
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--------------------------
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+---------------+
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|FPGA toolchains|
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+----^-----+----+
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+--+-----v--+
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+-------+ | |
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| Migen +--------> |
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+-------+ | | Your design
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| LiteX +---> ready to be used!
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+----------------------+ | |
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|LiteX Cores Ecosystem +--> |
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+----------------------+ +-^-------^-+
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(Eth, SATA, DRAM, PCIe, | |
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Video, etc...) + +
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board target
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file file
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LiteX already supports various softcores CPUs: LM32, Mor1kx, PicoRV32, VexRiscv
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and is compatible with the LiteX's Cores Ecosystem:
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- LiteDRAM: https://github.com/enjoy-digital/litedram
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- LiteEth: https://github.com/enjoy-digital/liteeth
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- LitePCIe: https://github.com/enjoy-digital/litepcie
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- LiteSATA: https://github.com/enjoy-digital/litesata
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- LiteSDCard: https://github.com/enjoy-digital/litesdcard
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- LiteICLink: https://github.com/enjoy-digital/liteiclink
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- LiteJESD204B: https://github.com/enjoy-digital/litejesd204b
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- LiteVideo: https://github.com/enjoy-digital/litevideo
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- LiteScope: https://github.com/enjoy-digital/litescope
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[> Sub-packages
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---------------
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gen:
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Provides specific or experimental modules to generate HDL that are not integrated
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in Migen.
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build:
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Provides tools to build FPGA bitstreams (interface to vendor toolchains) and to
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simulate HDL code or full SoCs.
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soc:
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Provides definitions/modules to build cores (bus, bank, flow), cores and tools
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to build a SoC from such cores.
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boards:
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Provides platforms and targets for the supported boards. All Migen's platforms
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can also be used in LiteX. The boards present in the LiteX repository are the
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official ones that are used for development/CI. More boards are available at:
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https://github.com/litex-hub/litex-boards
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[> Papers, Presentations, Tutorials, Links
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------------------------------------------
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FPGA lessons/tutorials:
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- https://github.com/enjoy-digital/fpga_101
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OSDA paper/slides:
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- https://osda.gitlab.io/19/1.1.pdf
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- https://osda.gitlab.io/19/1.1-slides.pdf
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Linux on LiteX-Vexriscv:
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- https://github.com/litex-hub/linux-on-litex-vexriscv
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RISC-V Getting Started Guide:
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- https://risc-v-getting-started-guide.readthedocs.io/en/latest/
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LiteX vs. Vivado First Impressions:
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- https://www.bunniestudios.com/blog/?p=5018
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35C3 - Snakes and Rabbits - How CCC shaped an open hardware success:
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- https://www.youtube.com/watch?v=AlmVxR0417c
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Tim has to many projects - LatchUp Edition:
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https://www.youtube.com/watch?v=v7WrTmexod0
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[> Very Quick start guide (for newcomers)
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-----------------------------------------
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TimVideos.us has done an awesome job for setting up a LiteX environment easily in
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the litex-buildenv repo: https://github.com/timvideos/litex-buildenv
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It's recommended for newcomers to go this way. Various FPGA boards are supported
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and multiple examples provided! You can even run Linux on your FPGA using LiteX
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very easily!
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Migen documentation can be found here: https://m-labs.hk/migen/manual
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[> Quick start guide (for advanced users)
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-----------------------------------------
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0. Install Python 3.5+ and FPGA vendor's development tools.
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1. Install Migen/LiteX and the LiteX's cores:
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wget https://raw.githubusercontent.com/enjoy-digital/litex/master/litex_setup.py
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chmod +x litex_setup.py
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./litex_setup.py init install --user (--user to install to user directory)
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Later, if you need to update all repositories:
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./litex_setup.py update
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2. Install a RISC-V toolchain:
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wget https://static.dev.sifive.com/dev-tools/riscv64-unknown-elf-gcc-8.1.0-2019.01.0-x86_64-linux-ubuntu14.tar.gz
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tar -xvf riscv64-unknown-elf-gcc-8.1.0-2019.01.0-x86_64-linux-ubuntu14.tar.gz
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export PATH=$PATH:$PWD/riscv64-unknown-elf-gcc-8.1.0-2019.01.0-x86_64-linux-ubuntu14/bin/
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3. Build the target of your board...:
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Go to litex-boards/litex_boards/**/targets (** being community/official/partner) and execute the target you want to build
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4. ... and/or install Verilator and test LiteX on your computer:
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Download and install Verilator: http://www.veripool.org/
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On Fedora:
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sudo dnf install libevent-devel json-c-devel
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On Ubuntu:
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sudo apt install libevent-dev libjson-c-dev
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run: litex_sim
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5. Run a terminal program on the board's serial port at 115200 8-N-1.
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You should get the BIOS prompt.
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[> Contact
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----------
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E-mail: florent [AT] enjoy-digital.fr
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