139 lines
3.9 KiB
Python
139 lines
3.9 KiB
Python
import random
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from migen.fhdl.std import *
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from migen.genlib.record import *
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from migen.sim.generic import run_simulation
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from lib.sata.common import *
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from lib.sata.link import SATALink
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from lib.sata.transport import SATATransport
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from lib.sata.command import SATACommand
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from lib.sata.test.bfm import *
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from lib.sata.test.common import *
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class CommandTXPacket(list):
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def __init__(self, write=0, read=0, identify=0, address=0, length=0, data=[]):
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self.ongoing = False
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self.done = False
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self.write = write
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self.read = read
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self.identify = identify
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self.address = address
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self.length = length
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for d in data:
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self.append(d)
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class CommandStreamer(Module):
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def __init__(self):
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self.source = Source(command_tx_description(32))
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###
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self.packets = []
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self.packet = CommandTXPacket()
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self.packet.done = 1
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self.length = 0
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def send(self, packet, blocking=True):
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self.packets.append(packet)
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if blocking:
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while packet.done == 0:
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yield
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def do_simulation(self, selfp):
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if len(self.packets) and self.packet.done:
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self.packet = self.packets.pop(0)
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selfp.source.write = self.packet.write
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selfp.source.read = self.packet.read
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selfp.source.identify = self.packet.identify
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selfp.source.address = self.packet.address
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selfp.source.length = self.packet.length
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if not self.packet.ongoing and not self.packet.done:
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selfp.source.stb = 1
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selfp.source.sop = 1
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if len(self.packet) > 0:
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selfp.source.data = self.packet.pop(0)
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self.packet.ongoing = True
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elif selfp.source.stb == 1 and selfp.source.ack == 1:
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selfp.source.sop = 0
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selfp.source.eop = (len(self.packet) == 1)
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if len(self.packet) > 0:
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selfp.source.stb = 1
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selfp.source.data = self.packet.pop(0)
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else:
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self.packet.done = 1
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selfp.source.stb = 0
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class CommandRXPacket(list):
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def __init__(self):
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self.ongoing = False
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self.done = False
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self.write = 0
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self.read = 0
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self.identify = 0
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self.success = 0
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self.failed = 0
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class CommandLogger(Module):
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def __init__(self):
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self.sink = Sink(command_rx_description(32))
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###
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self.packet = CommandRXPacket()
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def receive(self):
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self.packet.done = 0
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while self.packet.done == 0:
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yield
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def do_simulation(self, selfp):
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selfp.sink.ack = 1
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if selfp.sink.stb == 1 and selfp.sink.sop == 1:
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self.packet = CommandRXPacket()
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self.packet.write = selfp.sink.write
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self.packet.read = selfp.sink.read
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self.packet.identify = selfp.sink.identify
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self.packet.sucess = selfp.sink.success
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self.paclet.failed = selfp.sink.failed
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self.packet.append(selfp.sink.data)
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elif selfp.sink.stb:
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self.packet.append(selfp.sink.data)
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if (selfp.sink.stb ==1 and selfp.sink.eop ==1):
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self.packet.done = True
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class TB(Module):
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def __init__(self):
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self.submodules.bfm = BFM(phy_debug=False,
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link_random_level=0, link_debug=False,
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transport_debug=True, transport_loopback=False,
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command_debug=False,
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hdd_debug=False)
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self.submodules.link = SATALink(self.bfm.phy)
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self.submodules.transport = SATATransport(self.link)
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self.submodules.command = SATACommand(self.transport)
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self.submodules.streamer = CommandStreamer()
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self.submodules.logger = CommandLogger()
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self.comb += [
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Record.connect(self.streamer.source, self.command.sink),
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Record.connect(self.command.source, self.logger.sink)
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]
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def gen_simulation(self, selfp):
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self.bfm.hdd.allocate_mem(0x00000000, 64*1024*1024)
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selfp.command.source.ack = 1
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for i in range(100):
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yield
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streamer_packet = CommandTXPacket(write=1, address=1024, length=32, data=[i for i in range(32)])
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yield from self.streamer.send(streamer_packet)
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for i in range(32):
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yield
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streamer_packet = CommandTXPacket(read=1, address=1024, length=32)
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yield from self.streamer.send(streamer_packet)
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yield from self.logger.receive()
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for d in self.logger.packet:
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print("%08x" %d)
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if __name__ == "__main__":
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run_simulation(TB(), ncycles=512, vcd_name="my.vcd", keep_files=True)
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