Florent Kermarrec a18107f795 fhdl/verilog: Give more explict names to print functions.		2021-10-15 11:27:34 +02:00
..
build	build/efinix/efinity: Simplify get_pin_direction with direction/name already set to signals when generating the verilog.	2021-10-14 19:12:00 +02:00
compat	soc/add_spi_flash: Move integration code for previous LiteX SPI Flash core to compat/soc_add_spi_flash.py.	2021-07-29 18:48:03 +02:00
gen	fhdl/verilog: Give more explict names to print functions.	2021-10-15 11:27:34 +02:00
soc	soc_core: Also add "no_we" support to integrated_main_ram (and improve add_ram/add_rom calls).	2021-10-14 10:18:17 +02:00
tools	Merge pull request #1053 from rdolbeau/fb_rgb565	2021-10-08 14:15:10 +02:00
__init__.py	get_data_mod: Update pip to pip3 to avoid issues on systems with Python2 still installed.	2021-09-28 16:27:13 +02:00