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a1f7ecc8c5
litex
/
misoclib
/
mem
/
litesata
/
example_designs
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targets
History
Florent Kermarrec
a1f7ecc8c5
litesata: use 200MHz clock and SATA3 (6.0Gb/s) on all example designs: working :)
2015-06-10 12:15:59 +02:00
..
__init__.py
liteXXX cores: remove Identifier duplication
2015-03-01 11:24:58 +01:00
bist.py
litesata: use 200MHz clock and SATA3 (6.0Gb/s) on all example designs: working :)
2015-06-10 12:15:59 +02:00
core.py
litesata: do some cleanup and prepare for RAID
2015-05-23 14:08:56 +02:00
mirroring.py
litesata: use 200MHz clock and SATA3 (6.0Gb/s) on all example designs: working :)
2015-06-10 12:15:59 +02:00
striping.py
litesata: use 200MHz clock and SATA3 (6.0Gb/s) on all example designs: working :)
2015-06-10 12:15:59 +02:00