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litex/litex
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Florent Kermarrec a25645afa6 utils: add litex_read_verilog utility 
generate Migen's modules from verilog files
 		2018-11-16 16:09:44 +01:00
..
boards create utils directory and move the litex utils to it 2018-11-16 14:37:19 +01:00
build build/microsemi/libero_soc: able to generate design script (tcl) and design constraint (pdc) for libero soc / avalanche board. 2018-11-16 12:19:03 +01:00
gen gen: add common with reverse_bits/reverse_bytes functions 2018-10-30 10:15:29 +01:00
soc create utils directory and move the litex utils to it 2018-11-16 14:37:19 +01:00
utils utils: add litex_read_verilog utility 2018-11-16 16:09:44 +01:00
__init__.py ease RemoteClient import 2018-09-23 10:23:00 +02:00