202 lines
4.5 KiB
Python
202 lines
4.5 KiB
Python
from migen.fhdl.std import *
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from migen.genlib.cdc import MultiReg
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from migen.bank.description import *
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from migen.bank.eventmanager import *
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from migen.genlib.record import Record
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from migen.sim.generic import Simulator, TopLevel
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from migen.sim import icarus
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class UART(Module, AutoCSR):
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def __init__(self, pads, clk_freq, baud=115200):
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self._r_rxtx = CSR(8)
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self.submodules.ev = EventManager()
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self.ev.tx = EventSourceProcess()
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self.ev.rx = EventSourcePulse()
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self.ev.finalize()
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# Tuning word value
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tuning_word=int((baud/clk_freq)*2**32)
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self._r_tuning_word = CSRStorage(32, reset=tuning_word)
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###
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uart_clk_rxen = Signal()
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uart_clk_txen = Signal()
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phase_accumulator_rx = Signal(32)
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phase_accumulator_tx = Signal(32)
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pads.tx.reset = 1
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# TX
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tx_reg = Signal(8)
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tx_bitcount = Signal(4)
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tx_busy = self.ev.tx.trigger
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self.sync += [
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If(self._r_rxtx.re,
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tx_reg.eq(self._r_rxtx.r),
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tx_bitcount.eq(0),
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tx_busy.eq(1),
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pads.tx.eq(0)
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).Elif(uart_clk_txen & tx_busy,
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tx_bitcount.eq(tx_bitcount + 1),
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If(tx_bitcount == 8,
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pads.tx.eq(1)
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).Elif(tx_bitcount == 9,
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pads.tx.eq(1),
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tx_busy.eq(0)
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).Else(
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pads.tx.eq(tx_reg[0]),
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tx_reg.eq(Cat(tx_reg[1:], 0))
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)
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)
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]
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# RX
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rx = Signal()
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self.specials += MultiReg(pads.rx, rx)
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rx_r = Signal()
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rx_reg = Signal(8)
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rx_bitcount = Signal(4)
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rx_busy = Signal()
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rx_done = self.ev.rx.trigger
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rx_data = self._r_rxtx.w
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self.sync += [
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rx_done.eq(0),
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rx_r.eq(rx),
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If(~rx_busy,
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If(~rx & rx_r, # look for start bit
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rx_busy.eq(1),
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rx_bitcount.eq(0),
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)
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).Else(
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If(uart_clk_rxen,
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rx_bitcount.eq(rx_bitcount + 1),
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If(rx_bitcount == 0,
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If(rx, # verify start bit
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rx_busy.eq(0)
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)
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).Elif(rx_bitcount == 9,
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rx_busy.eq(0),
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If(rx, # verify stop bit
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rx_data.eq(rx_reg),
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rx_done.eq(1)
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)
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).Else(
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rx_reg.eq(Cat(rx_reg[1:], rx))
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)
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)
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)
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]
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self.sync += [
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If(rx_busy,
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Cat(phase_accumulator_rx, uart_clk_rxen).eq(phase_accumulator_rx + self._r_tuning_word.storage)
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).Else(
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Cat(phase_accumulator_rx, uart_clk_rxen).eq(2**31)
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),
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If(tx_busy,
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Cat(phase_accumulator_tx, uart_clk_txen).eq(phase_accumulator_tx + self._r_tuning_word.storage)
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).Else(
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Cat(phase_accumulator_tx, uart_clk_txen).eq(0)
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)
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]
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class UARTTB(Module):
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def __init__(self):
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MHz=1000000
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self.clk_freq = 83333333
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self.baud = 3*MHz
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self.pads = Record([("rx", 1), ("tx", 1)])
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self.submodules.slave = UART(self.pads, self.clk_freq, self.baud)
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def wait_for(self, ns_time):
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freq_in_ghz = self.clk_freq/(10**9)
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period = 1/freq_in_ghz
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num_loops = int(ns_time/period)
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for i in range(num_loops+1):
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yield
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def gen_simulation(self, selfp):
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baud_in_ghz = self.baud/(10**9)
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uart_period = int(1/baud_in_ghz)
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half_uart_period = int(1/(2*baud_in_ghz))
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# Set TX an RX lines idle
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selfp.pads.tx = 1
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selfp.pads.rx = 1
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yield
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# First send a few characters
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tx_string = "01234"
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print("Sending string: " + tx_string)
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for c in tx_string:
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while selfp.slave.ev.tx.trigger == 1:
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yield
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selfp.slave._r_rxtx.r = ord(c)
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selfp.slave._r_rxtx.re = 1
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yield
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selfp.slave._r_rxtx.re = 0
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yield from self.wait_for(half_uart_period)
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if selfp.pads.tx:
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print("FAILURE: no start bit sent")
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val = 0
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for i in range(8):
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yield from self.wait_for(uart_period)
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val >>= 1
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if selfp.pads.tx:
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val |= 0x80
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yield from self.wait_for(uart_period)
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if selfp.pads.tx == 0:
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print("FAILURE: no stop bit sent")
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if ord(c) != val:
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print("FAILURE: sent decimal value "+str(val)+" (char "+chr(val)+") instead of "+c)
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else:
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print("SUCCESS: sent "+c)
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# Then receive a character
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rx_string = '5'
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print("Receiving character "+rx_string)
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rx_value = ord(rx_string)
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for i in range(11):
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if (i == 0):
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# start bit
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selfp.pads.rx = 0
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elif (i == 9):
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# stop bit
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selfp.pads.rx = 1
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elif (i == 10):
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selfp.pads.rx = 1
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break
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else:
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selfp.pads.rx = 1 if (rx_value & 1) else 0
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rx_value >>= 1
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yield from self.wait_for(uart_period)
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rx_value = ord(rx_string)
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received_value = selfp.slave._r_rxtx.w
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if (received_value == rx_value):
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print("RX SUCCESS: ")
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else:
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print("RX FAILURE: ")
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print("received "+chr(received_value))
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while True:
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yield
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if __name__ == "__main__":
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with Simulator(UARTTB(), TopLevel("top.vcd", clk_period=int(1/0.08333333)), icarus.Runner(keep_files=False)) as s:
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s.run(20000)
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