Florent Kermarrec a3816096a7 cores/cpu: define CPUS and simplify instance		2019-09-28 00:55:08 +02:00
..
cores	cores/cpu: define CPUS and simplify instance	2019-09-28 00:55:08 +02:00
integration	cores/cpu: define CPUS and simplify instance	2019-09-28 00:55:08 +02:00
interconnect	wishbone2csr: refactor using FSM, reduce latency (make it asynchronous) and set csr.adr only when access is done (allow use of CSR/CSRBase we signal)	2019-09-24 17:55:29 +02:00
software	software/libbase/uart: add polling mode	2019-09-28 00:35:26 +02:00
__init__.py	litex: reorganize things, first work working version	2015-11-07 17:48:55 +01:00