100 lines
3.5 KiB
Python
100 lines
3.5 KiB
Python
import math
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from misoclib.mem.litesata.common import *
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from misoclib.mem.litesata.test.common import *
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from misoclib.mem.litesata.test.model.phy import *
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from misoclib.mem.litesata.test.model.link import *
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from misoclib.mem.litesata.test.model.transport import *
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from misoclib.mem.litesata.test.model.command import *
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def print_hdd(s, n=None):
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print_with_prefix(s, "[HDD{}]: ".format("" if n is None else str(n)))
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class HDDMemRegion:
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def __init__(self, base, count, sector_size):
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self.base = base
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self.count = count
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self.data = [0]*(count*sector_size//4)
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class HDD(Module):
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def __init__(self, n=None,
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link_debug=False, link_random_level=0,
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transport_debug=False, transport_loopback=False,
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hdd_debug=False,
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):
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self.n = n
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self.submodules.phy = PHYLayer()
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self.submodules.link = LinkLayer(self.phy, link_debug, link_random_level)
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self.submodules.transport = TransportLayer(self.link, transport_debug, transport_loopback)
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self.submodules.command = CommandLayer(self.transport)
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self.command.set_hdd(self)
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self.debug = hdd_debug
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self.mem = None
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self.wr_sector = 0
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self.wr_end_sector = 0
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self.rd_sector = 0
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self.rx_end_sector = 0
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def malloc(self, sector, count):
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if self.debug:
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s = "Allocating {n} sectors: {s} to {e}".format(n=count, s=sector, e=sector+count-1)
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s += " ({} KB)".format(count*logical_sector_size//1024)
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print_hdd(s, self.n)
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self.mem = HDDMemRegion(sector, count, logical_sector_size)
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def write(self, sector, data):
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n = math.ceil(dwords2sectors(len(data)))
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if self.debug:
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if n == 1:
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s = "{}".format(sector)
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else:
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s = "{s} to {e}".format(s=sector, e=sector+n-1)
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print_hdd("Writing sector " + s, self.n)
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for i in range(len(data)):
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offset = sectors2dwords(sector)
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self.mem.data[offset+i] = data[i]
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def read(self, sector, count):
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if self.debug:
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if count == 1:
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s = "{}".format(sector)
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else:
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s = "{s} to {e}".format(s=sector, e=sector+count-1)
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print_hdd("Reading sector " + s, self.n)
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data = []
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for i in range(sectors2dwords(count)):
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data.append(self.mem.data[sectors2dwords(sector)+i])
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return data
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def write_dma_callback(self, fis):
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self.wr_sector = fis.lba_lsb + (fis.lba_msb << 32)
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self.wr_end_sector = self.wr_sector + fis.count
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return [FIS_DMA_ACTIVATE_D2H()]
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def read_dma_callback(self, fis):
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self.rd_sector = fis.lba_lsb + (fis.lba_msb << 32)
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self.rd_end_sector = self.rd_sector + fis.count
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packets = []
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while self.rd_sector != self.rd_end_sector:
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count = min(self.rd_end_sector-self.rd_sector, (fis_max_dwords*4)//logical_sector_size)
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packet = self.read(self.rd_sector, count)
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packet.insert(0, 0)
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packets.append(FIS_DATA(packet, direction="D2H"))
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self.rd_sector += count
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packets.append(FIS_REG_D2H())
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return packets
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def data_callback(self, fis):
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self.write(self.wr_sector, fis.packet[1:])
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self.wr_sector += dwords2sectors(len(fis.packet[1:]))
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if self.wr_sector == self.wr_end_sector:
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return [FIS_REG_D2H()]
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else:
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return [FIS_DMA_ACTIVATE_D2H()]
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