205 lines
8.3 KiB
Python
205 lines
8.3 KiB
Python
from operator import itemgetter
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from migen.fhdl.std import *
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from migen.bank import csrgen
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from migen.bus import wishbone, csr, wishbone2csr
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from misoclib.com.uart.phy import UARTPHY
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from misoclib.com import uart
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from misoclib.cpu import lm32, mor1kx
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from misoclib.cpu import identifier, timer
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def mem_decoder(address, start=26, end=29):
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return lambda a: a[start:end] == ((address >> (start+2)) & (2**(end-start))-1)
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class SoC(Module):
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csr_map = {
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"crg": 0, # user
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"uart_phy": 1, # provided by default (optional)
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"uart": 2, # provided by default (optional)
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"identifier": 3, # provided by default (optional)
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"timer0": 4, # provided by default (optional)
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"buttons": 5, # user
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"leds": 6, # user
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}
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interrupt_map = {
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"uart": 0,
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"timer0": 1,
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}
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mem_map = {
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"rom": 0x00000000, # (default shadow @0x80000000)
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"sram": 0x10000000, # (default shadow @0x90000000)
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"main_ram": 0x40000000, # (default shadow @0xc0000000)
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"csr": 0x60000000, # (default shadow @0xe0000000)
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}
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def __init__(self, platform, clk_freq,
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cpu_type="lm32", cpu_reset_address=0x00000000,
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integrated_rom_size=0,
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integrated_sram_size=4096,
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integrated_main_ram_size=0,
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shadow_address=0x80000000,
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with_csr=True, csr_data_width=8, csr_address_width=14,
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with_uart=True, uart_baudrate=115200,
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with_identifier=True,
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with_timer=True):
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self.platform = platform
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self.clk_freq = clk_freq
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self.cpu_type = cpu_type
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if integrated_rom_size:
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cpu_reset_address = 0
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self.cpu_reset_address = cpu_reset_address
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self.integrated_rom_size = integrated_rom_size
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self.integrated_sram_size = integrated_sram_size
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self.integrated_main_ram_size = integrated_main_ram_size
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self.with_uart = with_uart
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self.uart_baudrate = uart_baudrate
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self.with_identifier = with_identifier
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self.shadow_address = shadow_address
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self.with_csr = with_csr
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self.csr_data_width = csr_data_width
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self.csr_address_width = csr_address_width
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self._memory_regions = [] # list of (name, origin, length)
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self._csr_regions = [] # list of (name, origin, busword, csr_list/Memory)
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self._constants = [] # list of (name, value)
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self._wb_masters = []
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self._wb_slaves = []
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if cpu_type != "none":
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if cpu_type == "lm32":
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self.add_cpu_or_bridge(lm32.LM32(platform, self.cpu_reset_address))
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elif cpu_type == "or1k":
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self.add_cpu_or_bridge(mor1kx.MOR1KX(platform, self.cpu_reset_address))
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else:
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raise ValueError("Unsupported CPU type: {}".format(cpu_type))
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self.add_wb_master(self.cpu_or_bridge.ibus)
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self.add_wb_master(self.cpu_or_bridge.dbus)
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if integrated_rom_size:
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self.submodules.rom = wishbone.SRAM(integrated_rom_size, read_only=True)
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self.register_rom(self.rom.bus, integrated_rom_size)
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if integrated_sram_size:
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self.submodules.sram = wishbone.SRAM(integrated_sram_size)
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self.register_mem("sram", self.mem_map["sram"], self.sram.bus, integrated_sram_size)
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# Note: Main Ram can be used when no external SDRAM is available and use SDRAM mapping.
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if integrated_main_ram_size:
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self.submodules.main_ram = wishbone.SRAM(integrated_main_ram_size)
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self.register_mem("main_ram", self.mem_map["main_ram"], self.main_ram.bus, integrated_main_ram_size)
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if with_csr:
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self.submodules.wishbone2csr = wishbone2csr.WB2CSR(bus_csr=csr.Interface(csr_data_width, csr_address_width))
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self.register_mem("csr", self.mem_map["csr"], self.wishbone2csr.wishbone)
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if with_uart:
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self.submodules.uart_phy = UARTPHY(platform.request("serial"), clk_freq, uart_baudrate)
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self.submodules.uart = uart.UART(self.uart_phy)
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if with_identifier:
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platform_id = 0x554E if not hasattr(platform, "identifier") else platform.identifier
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self.submodules.identifier = identifier.Identifier(platform_id, int(clk_freq))
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if with_timer:
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self.submodules.timer0 = timer.Timer()
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def add_cpu_or_bridge(self, cpu_or_bridge):
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if self.finalized:
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raise FinalizeError
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if hasattr(self, "cpu_or_bridge"):
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raise NotImplementedError("More than one CPU is not supported")
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self.submodules.cpu_or_bridge = cpu_or_bridge
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def init_rom(self, data):
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self.rom.mem.init = data
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def add_wb_master(self, wbm):
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if self.finalized:
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raise FinalizeError
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self._wb_masters.append(wbm)
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def add_wb_slave(self, address_decoder, interface):
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if self.finalized:
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raise FinalizeError
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self._wb_slaves.append((address_decoder, interface))
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def add_memory_region(self, name, origin, length):
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def in_this_region(addr):
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return addr >= origin and addr < origin + length
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for n, o, l in self._memory_regions:
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if n == name or in_this_region(o) or in_this_region(o+l-1):
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raise ValueError("Memory region conflict between {} and {}".format(n, name))
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self._memory_regions.append((name, origin, length))
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def register_mem(self, name, address, interface, size=None):
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self.add_wb_slave(mem_decoder(address), interface)
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if size is not None:
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self.add_memory_region(name, address, size)
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def register_rom(self, interface, rom_size=0xa000):
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self.add_wb_slave(mem_decoder(self.mem_map["rom"]), interface)
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self.add_memory_region("rom", self.cpu_reset_address, rom_size)
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def get_memory_regions(self):
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return self._memory_regions
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def check_csr_region(self, name, origin):
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for n, o, l, obj in self._csr_regions:
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if n == name or o == origin:
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raise ValueError("CSR region conflict between {} and {}".format(n, name))
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def add_csr_region(self, name, origin, busword, obj):
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self.check_csr_region(name, origin)
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self._csr_regions.append((name, origin, busword, obj))
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def get_csr_regions(self):
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return self._csr_regions
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def add_constant(self, name, value):
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self._constants.append((name, value))
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def get_constants(self):
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r = []
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for name, interrupt in sorted(self.interrupt_map.items(), key=itemgetter(1)):
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r.append((name.upper() + "_INTERRUPT", interrupt))
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r += self._constants
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return r
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def do_finalize(self):
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registered_mems = {regions[0] for regions in self._memory_regions}
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if self.cpu_type != "none":
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for mem in "rom", "sram":
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if mem not in registered_mems:
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raise FinalizeError("CPU needs a {} to be registered with SoC.register_mem()".format(mem))
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# Wishbone
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self.submodules.wishbonecon = wishbone.InterconnectShared(self._wb_masters,
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self._wb_slaves, register=True)
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# CSR
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if self.with_csr:
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self.submodules.csrbankarray = csrgen.BankArray(self,
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lambda name, memory: self.csr_map[name if memory is None else name + "_" + memory.name_override],
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data_width=self.csr_data_width, address_width=self.csr_address_width)
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self.submodules.csrcon = csr.Interconnect(self.wishbone2csr.csr, self.csrbankarray.get_buses())
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for name, csrs, mapaddr, rmap in self.csrbankarray.banks:
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self.add_csr_region(name, self.mem_map["csr"]+self.shadow_address+0x800*mapaddr, self.csr_data_width, csrs)
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for name, memory, mapaddr, mmap in self.csrbankarray.srams:
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self.add_csr_region(name + "_" + memory.name_override, self.mem_map["csr"]+self.shadow_address+0x800*mapaddr, self.csr_data_width, memory)
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# Interrupts
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if hasattr(self.cpu_or_bridge, "interrupt"):
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for k, v in sorted(self.interrupt_map.items(), key=itemgetter(1)):
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if hasattr(self, k):
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self.comb += self.cpu_or_bridge.interrupt[v].eq(getattr(self, k).ev.irq)
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