Hardware/litex
1
0
Fork 0
mirror of https://github.com/enjoy-digital/litex.git synced 2025-01-04 09:52:26 -05:00
Code Issues Projects Releases Packages Wiki Activity
litex/misoclib/com/litepcie/example_designs
History
Florent Kermarrec a99aa9c7fd uart: rename wishbone to bridge
2015-05-09 16:24:28 +02:00
..
build
targets uart: rename wishbone to bridge 2015-05-09 16:24:28 +02:00
test
__init__.py
make.py