Florent Kermarrec a559fc77c8 remove upload optimization (we will use wishbone later for performance)		2015-02-24 18:01:04 +01:00
..
bridge	uart2wb: copy UARTTX/UARTRX from MiSoC to avoid dependency	2015-02-02 14:23:01 +01:00
core	remove upload optimization (we will use wishbone later for performance)	2015-02-24 18:01:04 +01:00
frontend	rle: increase dw automatically when needed	2015-02-23 09:41:18 +01:00
host	remove upload optimization (we will use wishbone later for performance)	2015-02-24 18:01:04 +01:00
__init__.py	start refactoring and change name to LiteScope	2015-01-23 00:02:53 +01:00
common.py	simplify code and use Sink/Source instead of records	2015-01-25 15:58:00 +01:00