64 lines
1.7 KiB
Python
64 lines
1.7 KiB
Python
from migen.genlib.resetsync import AsyncResetSynchronizer
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from litesata.common import *
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from litesata.phy import LiteSATAPHY
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from litesata import LiteSATA
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class _CRG(Module):
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def __init__(self, platform):
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self.cd_sys = ClockDomain()
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self.reset = Signal()
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self.comb += self.cd_sys.clk.eq(platform.request("sys_clk"))
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self.specials += [
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AsyncResetSynchronizer(self.cd_sys, platform.request("sys_rst") | self.reset),
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]
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class LiteSATACore(Module):
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default_platform = "verilog_backend"
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def __init__(self, platform):
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clk_freq = 166*1000000
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self.crg = _CRG(platform)
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# SATA PHY/Core/Frontend
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self.sata_phy = LiteSATAPHY(platform.device, platform.request("sata"), "SATA2", clk_freq)
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self.comb += self.crg.reset.eq(self.sata_phy.ctrl.need_reset) # XXX FIXME
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self.sata = LiteSATA(self.sata_phy, with_crossbar=True)
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# Get user ports from crossbar
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n = 4
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self.crossbar_ports = self.sata.crossbar.get_ports(n)
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def get_ios(self):
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# clock / reset
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ios = {self.crg.cd_sys.clk, self.crg.cd_sys.rst}
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# Transceiver
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for e in dir(self.sata_phy.pads):
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obj = getattr(self.sata_phy.pads, e)
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if isinstance(obj, Signal):
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ios = ios.union({obj})
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# User ports
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def _iter_layout(layout):
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for e in layout:
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if isinstance(e[1], list):
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yield from _iter_layout(e[1])
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else:
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yield e
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sink_layout = command_tx_description(32).get_full_layout()
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source_layout = command_rx_description(32).get_full_layout()
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for crossbar_port in self.crossbar_ports:
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for e in _iter_layout(sink_layout):
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obj = getattr(crossbar_port.source, e[0])
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ios = ios.union({obj})
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for e in _iter_layout(source_layout):
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obj = getattr(crossbar_port.sink, e[0])
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ios = ios.union({obj})
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return ios
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default_subtarget = LiteSATACore
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