Florent Kermarrec a5d0a340c3 test: specify wishbone adr_width on AXI(Lite)<-->Wishbone tests and remove debug traces.		2020-08-04 09:39:23 +02:00
..
cores	cores/cpu/rocket: expose slave port for DMA	2020-08-03 16:14:11 -04:00
doc	litex: add sphinx_extra_config to generate_docs()	2020-07-24 16:01:54 +08:00
integration	integration/soc: make DMA slave region cover (at least) the lower 4GB	2020-08-03 16:14:11 -04:00
interconnect	test: specify wishbone adr_width on AXI(Lite)<-->Wishbone tests and remove debug traces.	2020-08-04 09:39:23 +02:00
software	liblitesdcard/sdcard: (temporarily) slow down SDCARD_CLK_FREQ to 25MHz	2020-08-03 16:14:11 -04:00
__init__.py	litex: reorganize things, first work working version	2015-11-07 17:48:55 +01:00