104 lines
3.2 KiB
Python
104 lines
3.2 KiB
Python
#
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# This file is part of LiteX.
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#
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# Copyright (c) 2020 Florent Kermarrec <florent@enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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import unittest
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from litex.soc.cores.clock import *
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class TestClock(unittest.TestCase):
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# Xilinx / Spartan 6
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def test_s6pll(self):
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pll = S6PLL()
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pll.register_clkin(Signal(), 100e6)
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for i in range(pll.nclkouts_max):
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pll.create_clkout(ClockDomain("clkout{}".format(i)), 200e6)
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pll.compute_config()
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def test_s6dcm(self):
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dcm = S6DCM()
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dcm.register_clkin(Signal(), 100e6)
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for i in range(dcm.nclkouts_max):
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dcm.create_clkout(ClockDomain("clkout{}".format(i)), 200e6)
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dcm.compute_config()
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# Xilinx / 7-Series
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def test_s7pll(self):
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pll = S7PLL()
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pll.register_clkin(Signal(), 100e6)
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for i in range(pll.nclkouts_max):
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pll.create_clkout(ClockDomain("clkout{}".format(i)), 200e6)
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pll.compute_config()
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def test_s7mmcm(self):
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mmcm = S7MMCM()
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mmcm.register_clkin(Signal(), 100e6)
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for i in range(mmcm.nclkouts_max):
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mmcm.create_clkout(ClockDomain("clkout{}".format(i)), 200e6)
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mmcm.compute_config()
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# Xilinx / Ultrascale
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def test_uspll(self):
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pll = USPLL()
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pll.register_clkin(Signal(), 100e6)
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for i in range(pll.nclkouts_max):
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pll.create_clkout(ClockDomain("clkout{}".format(i)), 200e6)
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pll.compute_config()
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def test_usmmcm(self):
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mmcm = USMMCM()
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mmcm.register_clkin(Signal(), 100e6)
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for i in range(mmcm.nclkouts_max):
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mmcm.create_clkout(ClockDomain("clkout{}".format(i)), 200e6)
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mmcm.compute_config()
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# Xilinx / Ultrascale Plus
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def test_usppll(self):
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pll = USPPLL()
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pll.register_clkin(Signal(), 100e6)
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for i in range(pll.nclkouts_max):
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pll.create_clkout(ClockDomain("clkout{}".format(i)), 200e6)
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pll.compute_config()
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def test_uspmmcm(self):
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mmcm = USPMMCM()
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mmcm.register_clkin(Signal(), 100e6)
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for i in range(mmcm.nclkouts_max):
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mmcm.create_clkout(ClockDomain("clkout{}".format(i)), 200e6)
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mmcm.compute_config()
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# Lattice / iCE40
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def test_ice40pll(self):
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pll = USMMCM()
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pll.register_clkin(Signal(), 100e6)
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for i in range(pll.nclkouts_max):
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pll.create_clkout(ClockDomain("clkout{}".format(i)), 200e6)
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pll.compute_config()
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# Lattice / ECP5
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def test_ecp5pll(self):
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pll = ECP5PLL()
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pll.register_clkin(Signal(), 100e6)
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for i in range(pll.nclkouts_max):
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pll.create_clkout(ClockDomain("clkout{}".format(i)), 200e6)
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pll.compute_config()
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# Altera / CycloneIV
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def test_cycloneivpll(self):
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pll = CycloneIVPLL()
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pll.register_clkin(Signal(), 50e6)
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for i in range(pll.nclkouts_max):
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pll.create_clkout(ClockDomain("clkout{}".format(i)), 100e6)
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pll.compute_config()
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# Altera / CycloneV
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def test_cyclonevpll(self):
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pll = CycloneVPLL()
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pll.register_clkin(Signal(), 50e6)
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for i in range(pll.nclkouts_max):
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pll.create_clkout(ClockDomain("clkout{}".format(i)), 100e6)
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pll.compute_config()
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