298 lines
6.4 KiB
Python
298 lines
6.4 KiB
Python
from migen.fhdl.structure import *
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from migen.fhdl.module import *
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from migen.genlib.record import *
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from migen.genlib.cdc import MultiReg
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from migen.genlib.fsm import FSM, NextState
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from migen.genlib.misc import split, displacer, chooser
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from migen.bank.description import *
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from migen.bus import wishbone
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# Todo
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# ----
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# - implement timeout in fsm to prevent deadlocks
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def rec_rx():
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layout = [
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("stb", 1, DIR_M_TO_S),
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("dat", 8, DIR_M_TO_S)
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]
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return Record(layout)
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def rec_tx():
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layout = [
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("stb", 1, DIR_M_TO_S),
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("ack", 1, DIR_S_TO_M),
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("dat", 8, DIR_M_TO_S)
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]
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return Record(layout)
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class UART(Module):
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def __init__(self, pads, clk_freq, baud=115200):
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self.rx = rec_rx()
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self.tx = rec_tx()
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self.divisor = Signal(16, reset=int(clk_freq/baud/16))
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pads.tx.reset = 1
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###
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enable16 = Signal()
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enable16_counter = Signal(16)
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self.comb += enable16.eq(enable16_counter == 0)
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self.sync += [
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enable16_counter.eq(enable16_counter - 1),
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If(enable16,
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enable16_counter.eq(self.divisor - 1))
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]
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# TX
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tx_reg = Signal(8)
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tx_bitcount = Signal(4)
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tx_count16 = Signal(4)
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tx_done = self.tx.ack
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tx_busy = Signal()
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tx_stb_d = Signal()
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self.sync += [
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tx_stb_d.eq(self.tx.stb & ~tx_done),
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tx_done.eq(0),
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If(self.tx.stb & ~tx_stb_d,
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tx_reg.eq(self.tx.dat),
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tx_bitcount.eq(0),
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tx_count16.eq(1),
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tx_busy.eq(1),
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pads.tx.eq(0)
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).Elif(enable16 & tx_busy,
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tx_count16.eq(tx_count16 + 1),
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If(tx_count16 == 0,
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tx_bitcount.eq(tx_bitcount + 1),
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If(tx_bitcount == 8,
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pads.tx.eq(1)
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).Elif(tx_bitcount == 9,
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pads.tx.eq(1),
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tx_busy.eq(0),
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tx_done.eq(1)
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).Else(
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pads.tx.eq(tx_reg[0]),
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tx_reg.eq(Cat(tx_reg[1:], 0))
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)
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)
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)
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]
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# RX
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rx = Signal()
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self.specials += MultiReg(pads.rx, rx, "sys")
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rx_r = Signal()
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rx_reg = Signal(8)
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rx_bitcount = Signal(4)
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rx_count16 = Signal(4)
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rx_busy = Signal()
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rx_done = self.rx.stb
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rx_data = self.rx.dat
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self.sync += [
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rx_done.eq(0),
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If(enable16,
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rx_r.eq(rx),
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If(~rx_busy,
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If(~rx & rx_r, # look for start bit
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rx_busy.eq(1),
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rx_count16.eq(7),
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rx_bitcount.eq(0)
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)
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).Else(
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rx_count16.eq(rx_count16 + 1),
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If(rx_count16 == 0,
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rx_bitcount.eq(rx_bitcount + 1),
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If(rx_bitcount == 0,
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If(rx, # verify start bit
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rx_busy.eq(0)
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)
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).Elif(rx_bitcount == 9,
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rx_busy.eq(0),
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If(rx, # verify stop bit
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rx_data.eq(rx_reg),
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rx_done.eq(1)
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)
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).Else(
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rx_reg.eq(Cat(rx_reg[1:], rx))
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)
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)
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)
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)
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]
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class Counter(Module):
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def __init__(self, width):
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self.value = Signal(width)
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self.clr = Signal()
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self.inc = Signal()
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self.sync += [
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If(self.clr,
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self.value.eq(0)
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).Elif(self.inc,
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self.value.eq(self.value+1)
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)
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]
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class UARTPads:
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def __init__(self):
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self.rx = Signal()
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self.tx = Signal()
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class UARTMux(Module):
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def __init__(self, pads, nb):
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self.sel = Signal(max=nb)
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self.pads = [UARTPads() for i in range(nb)]
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###
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# Route Rx pad to all modules
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for i in range(nb):
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self.comb += self.pads[i].rx.eq(pads.rx)
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# Route only selected module to Tx pad
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pads_tx = [self.pads[i].tx for i in range(nb)]
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self.comb += chooser(Cat(pads_tx), self.sel, pads.tx, n=nb)
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class UART2Wishbone(Module, AutoCSR):
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WRITE_CMD = 0x01
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READ_CMD = 0x02
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def __init__(self, pads, clk_freq, baud=115200, share_uart=False):
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# Wishbone interface
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self.wishbone = wishbone.Interface()
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if share_uart:
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self._sel = CSRStorage()
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###
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if share_uart:
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self.submodules.uart_mux = UARTMux(pads, 2)
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self.submodules.uart = UART(self.uart_mux.pads[1], clk_freq, baud)
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self.shared_pads = self.uart_mux.pads[0]
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self.comb += self.uart_mux.sel.eq(self._sel.storage)
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else:
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self.submodules.uart = UART(pads, clk_freq, baud)
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uart = self.uart
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fsm = FSM()
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self.submodules += fsm
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word_cnt = Counter(3)
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burst_cnt = Counter(8)
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self.submodules += word_cnt, burst_cnt
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###
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cmd = Signal(8)
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fsm.act("WAIT_CMD",
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If(uart.rx.stb,
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If( (uart.rx.dat == self.WRITE_CMD) |
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(uart.rx.dat == self.READ_CMD),
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NextState("RECEIVE_BURST_LENGTH")
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),
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word_cnt.clr.eq(1),
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burst_cnt.clr.eq(1)
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)
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)
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self.sync += If(fsm.ongoing("WAIT_CMD") & uart.rx.stb, cmd.eq(uart.rx.dat))
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####
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burst_length = Signal(8)
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fsm.act("RECEIVE_BURST_LENGTH",
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word_cnt.inc.eq(uart.rx.stb),
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If(word_cnt.value == 1,
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word_cnt.clr.eq(1),
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NextState("RECEIVE_ADDRESS")
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)
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)
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self.sync += \
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If(fsm.ongoing("RECEIVE_BURST_LENGTH") & uart.rx.stb, burst_length.eq(uart.rx.dat))
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####
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address = Signal(32)
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fsm.act("RECEIVE_ADDRESS",
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word_cnt.inc.eq(uart.rx.stb),
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If(word_cnt.value == 4,
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word_cnt.clr.eq(1),
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If(cmd == self.WRITE_CMD,
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NextState("RECEIVE_DATA")
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).Elif(cmd == self.READ_CMD,
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NextState("READ_DATA")
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)
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)
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)
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self.sync += \
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If(fsm.ongoing("RECEIVE_ADDRESS") & uart.rx.stb,
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address.eq(Cat(uart.rx.dat, address[0:24]))
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)
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###
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data = Signal(32)
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###
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fsm.act("RECEIVE_DATA",
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word_cnt.inc.eq(uart.rx.stb),
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If(word_cnt.value == 4,
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word_cnt.clr.eq(1),
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NextState("WRITE_DATA")
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)
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)
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fsm.act("WRITE_DATA",
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self.wishbone.adr.eq(address + burst_cnt.value),
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self.wishbone.dat_w.eq(data),
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self.wishbone.sel.eq(2**flen(self.wishbone.sel)-1),
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self.wishbone.stb.eq(1),
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self.wishbone.we.eq(1),
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self.wishbone.cyc.eq(1),
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If(self.wishbone.ack,
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burst_cnt.inc.eq(1),
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If(burst_cnt.value == (burst_length-1),
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NextState("WAIT_CMD")
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).Else(
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word_cnt.clr.eq(1),
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NextState("RECEIVE_DATA")
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)
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)
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)
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###
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fsm.act("READ_DATA",
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self.wishbone.adr.eq(address + burst_cnt.value),
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self.wishbone.sel.eq(2**flen(self.wishbone.sel)-1),
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self.wishbone.stb.eq(1),
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self.wishbone.we.eq(0),
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self.wishbone.cyc.eq(1),
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If(self.wishbone.stb & self.wishbone.ack,
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word_cnt.clr.eq(1),
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NextState("SEND_DATA")
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)
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)
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fsm.act("SEND_DATA",
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word_cnt.inc.eq(uart.tx.ack),
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If(word_cnt.value == 4,
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burst_cnt.inc.eq(1),
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If(burst_cnt.value == (burst_length-1),
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NextState("WAIT_CMD")
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).Else(
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NextState("READ_DATA")
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)
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),
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uart.tx.stb.eq(1),
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chooser(data, word_cnt.value, uart.tx.dat, n=4, reverse=True)
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)
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###
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self.sync += \
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If(fsm.ongoing("RECEIVE_DATA") & uart.rx.stb,
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data.eq(Cat(uart.rx.dat, data[0:24]))
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).Elif(fsm.ongoing("READ_DATA") & self.wishbone.stb & self.wishbone.ack,
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data.eq(self.wishbone.dat_r)
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)
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