281 lines
7.1 KiB
Python
281 lines
7.1 KiB
Python
from lib.sata.common import *
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tx_to_rx = [
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("write", 1),
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("read", 1),
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("identify", 1),
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("count", 4)
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]
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rx_to_tx = [
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("dma_activate", 1),
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("data", 1),
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("reg_d2h", 1)
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]
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class SATACommandTX(Module):
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def __init__(self, transport, sector_size):
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self.sink = sink = Sink(command_tx_description(32))
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self.to_rx = to_rx = Source(tx_to_rx)
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self.from_rx = from_rx = Sink(rx_to_tx)
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###
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self.comb += [
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transport.sink.pm_port.eq(0),
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transport.sink.features.eq(0),
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transport.sink.lba.eq(sink.sector),
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transport.sink.device.eq(0xe0),
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transport.sink.count.eq(sink.count),
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transport.sink.icc.eq(0),
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transport.sink.control.eq(0),
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]
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fsm = FSM(reset_state="IDLE")
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self.submodules += fsm
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fsm.act("IDLE",
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If(sink.stb & sink.sop,
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If(sink.write,
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NextState("SEND_WRITE_DMA_CMD")
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).Elif(sink.read,
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NextState("SEND_READ_DMA_CMD")
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).Elif(sink.identify,
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NextState("SEND_IDENTIFY_CMD")
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).Else(
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sink.ack.eq(1)
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)
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).Else(
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sink.ack.eq(1)
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)
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)
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fsm.act("SEND_WRITE_DMA_CMD",
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transport.sink.stb.eq(sink.stb),
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transport.sink.sop.eq(1),
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transport.sink.eop.eq(1),
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transport.sink.type.eq(fis_types["REG_H2D"]),
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transport.sink.c.eq(1),
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transport.sink.command.eq(regs["WRITE_DMA_EXT"]),
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If(sink.stb & transport.sink.ack,
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NextState("WAIT_DMA_ACTIVATE")
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)
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)
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fsm.act("WAIT_DMA_ACTIVATE",
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If(from_rx.dma_activate,
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NextState("SEND_DATA")
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)
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)
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fsm.act("SEND_DATA",
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transport.sink.stb.eq(sink.stb),
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transport.sink.sop.eq(sink.sop),
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transport.sink.eop.eq(sink.eop),
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transport.sink.type.eq(fis_types["DATA"]),
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transport.sink.data.eq(sink.data),
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sink.ack.eq(transport.sink.ack),
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If(sink.stb & sink.ack & sink.eop,
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NextState("IDLE")
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)
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)
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fsm.act("SEND_READ_DMA_CMD",
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transport.sink.stb.eq(sink.stb),
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transport.sink.sop.eq(1),
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transport.sink.eop.eq(1),
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transport.sink.type.eq(fis_types["REG_H2D"]),
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transport.sink.c.eq(1),
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transport.sink.command.eq(regs["READ_DMA_EXT"]),
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sink.ack.eq(transport.sink.ack),
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If(sink.stb & sink.ack,
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NextState("IDLE")
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)
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)
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fsm.act("SEND_IDENTIFY_CMD",
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transport.sink.stb.eq(sink.stb),
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transport.sink.sop.eq(1),
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transport.sink.eop.eq(1),
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transport.sink.type.eq(fis_types["REG_H2D"]),
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transport.sink.c.eq(1),
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transport.sink.command.eq(regs["IDENTIFY_DEVICE_DMA"]),
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sink.ack.eq(transport.sink.ack),
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If(sink.stb & sink.ack,
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NextState("IDLE")
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)
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)
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self.comb += [
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If(sink.stb,
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to_rx.write.eq(sink.write),
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to_rx.read.eq(sink.read),
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to_rx.identify.eq(sink.identify),
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to_rx.count.eq(sink.count)
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)
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]
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class SATACommandRX(Module):
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def __init__(self, transport, sector_size, max_count):
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self.source = source = Source(command_rx_description(32))
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self.to_tx = to_tx = Source(rx_to_tx)
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self.from_tx = from_tx = Sink(tx_to_rx)
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###
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cmd_fifo = SyncFIFO(command_rx_cmd_description(32), 2) # Note: ideally depth=1
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data_fifo = InsertReset(SyncFIFO(command_rx_data_description(32), sector_size*max_count//4, buffered=True))
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self.submodules += cmd_fifo, data_fifo
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def test_type(name):
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return transport.source.type == fis_types[name]
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dma_activate = Signal()
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fsm = FSM(reset_state="IDLE")
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self.submodules += fsm
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fsm.act("IDLE",
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transport.source.ack.eq(1),
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If(from_tx.write,
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NextState("WAIT_WRITE_ACTIVATE")
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).Elif(from_tx.read | from_tx.identify,
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NextState("WAIT_READ_DATA")
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)
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)
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identify = Signal()
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self.sync += \
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If(fsm.ongoing("IDLE"),
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identify.eq(from_tx.identify)
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)
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fsm.act("WAIT_WRITE_ACTIVATE",
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transport.source.ack.eq(1),
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If(transport.source.stb,
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If(test_type("DMA_ACTIVATE_D2H"),
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dma_activate.eq(1),
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NextState("WAIT_WRITE_REG_D2H")
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)
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)
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)
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fsm.act("WAIT_WRITE_REG_D2H",
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transport.source.ack.eq(1),
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If(transport.source.stb,
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If(test_type("REG_D2H"),
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NextState("PRESENT_WRITE_RESPONSE")
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)
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)
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)
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fsm.act("PRESENT_WRITE_RESPONSE",
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cmd_fifo.sink.stb.eq(1),
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cmd_fifo.sink.write.eq(1),
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cmd_fifo.sink.success.eq(1),
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If(cmd_fifo.sink.stb & cmd_fifo.sink.ack,
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NextState("IDLE")
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)
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)
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fsm.act("WAIT_READ_DATA",
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transport.source.ack.eq(1),
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If(transport.source.stb,
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transport.source.ack.eq(0),
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If(test_type("DATA"),
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NextState("PRESENT_READ_DATA")
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)
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)
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)
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fsm.act("PRESENT_READ_DATA",
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data_fifo.sink.stb.eq(transport.source.stb),
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data_fifo.sink.sop.eq(transport.source.sop),
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data_fifo.sink.eop.eq(transport.source.eop),
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data_fifo.sink.data.eq(transport.source.data),
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transport.source.ack.eq(data_fifo.sink.ack),
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If(data_fifo.sink.stb & data_fifo.sink.eop & data_fifo.sink.ack,
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NextState("WAIT_READ_REG_D2H")
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)
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)
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fsm.act("WAIT_READ_REG_D2H",
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transport.source.ack.eq(1),
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If(transport.source.stb,
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If(test_type("REG_D2H"),
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NextState("PRESENT_READ_RESPONSE")
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)
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)
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)
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fsm.act("PRESENT_READ_RESPONSE",
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cmd_fifo.sink.stb.eq(1),
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cmd_fifo.sink.read.eq(~identify),
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cmd_fifo.sink.identify.eq(identify),
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cmd_fifo.sink.success.eq(1),
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cmd_fifo.sink.failed.eq(0),
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If(~cmd_fifo.fifo.readable, # Note: simulate a depth=1 fifo
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If(cmd_fifo.sink.stb & cmd_fifo.sink.ack,
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If(cmd_fifo.sink.failed,
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data_fifo.reset.eq(1)
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),
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NextState("IDLE")
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)
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)
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)
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out_fsm = FSM(reset_state="IDLE")
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self.submodules += out_fsm
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out_fsm.act("IDLE",
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If(cmd_fifo.source.stb & cmd_fifo.source.write,
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NextState("PRESENT_WRITE_RESPONSE"),
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).Elif(cmd_fifo.source.stb & (cmd_fifo.source.read | cmd_fifo.source.identify),
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If(cmd_fifo.source.success,
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NextState("PRESENT_READ_RESPONSE_SUCCESS"),
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).Else(
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NextState("PRESENT_READ_RESPONSE_FAILED"),
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)
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)
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)
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out_fsm.act("PRESENT_WRITE_RESPONSE",
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source.stb.eq(1),
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source.sop.eq(1),
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source.eop.eq(1),
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source.write.eq(1),
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source.success.eq(cmd_fifo.source.success),
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If(source.stb & source.ack,
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cmd_fifo.source.ack.eq(1),
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NextState("IDLE")
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)
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)
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out_fsm.act("PRESENT_READ_RESPONSE_SUCCESS",
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source.stb.eq(data_fifo.source.stb),
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source.read.eq(cmd_fifo.source.read),
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source.identify.eq(cmd_fifo.source.identify),
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source.success.eq(1),
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source.sop.eq(data_fifo.source.sop),
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source.eop.eq(data_fifo.source.eop),
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source.data.eq(data_fifo.source.data),
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data_fifo.source.ack.eq(source.ack),
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If(source.stb & source.eop & source.ack,
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cmd_fifo.source.ack.eq(1),
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NextState("IDLE")
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)
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)
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out_fsm.act("PRESENT_READ_RESPONSE_FAILED",
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source.stb.eq(1),
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source.sop.eq(1),
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source.eop.eq(1),
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source.read.eq(cmd_fifo.source.read),
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source.identify.eq(cmd_fifo.source.identify),
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source.failed.eq(1),
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If(source.stb & source.ack,
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cmd_fifo.source.ack.eq(1),
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NextState("IDLE")
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)
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)
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self.comb += [
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to_tx.dma_activate.eq(dma_activate),
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]
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class SATACommand(Module):
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def __init__(self, transport, sector_size=512, max_count=4):
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if max_count*sector_size > 8192:
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raise ValueError("sector_size * max_count must be <= 8192")
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self.tx = SATACommandTX(transport, sector_size)
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self.rx = SATACommandRX(transport, sector_size, max_count)
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self.comb += [
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self.rx.to_tx.connect(self.tx.from_rx),
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self.tx.to_rx.connect(self.rx.from_tx)
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]
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self.sink, self.source = self.tx.sink, self.rx.source
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