Florent Kermarrec 741ecca5b4 la: fix intput_buffer clocking when clk_domain is not "sys"		2015-02-19 11:41:54 +01:00
..
bridge	uart2wb: copy UARTTX/UARTRX from MiSoC to avoid dependency	2015-02-02 14:23:01 +01:00
core	fix rle when used with subsampler	2015-02-19 11:34:20 +01:00
frontend	la: fix intput_buffer clocking when clk_domain is not "sys"	2015-02-19 11:41:54 +01:00
host	driver/la: add samplerate computation (required by sigrok export)	2015-02-19 11:16:32 +01:00
__init__.py	start refactoring and change name to LiteScope	2015-01-23 00:02:53 +01:00
common.py	simplify code and use Sink/Source instead of records	2015-01-25 15:58:00 +01:00