150 lines
4.6 KiB
Python
150 lines
4.6 KiB
Python
from migen.bus import wishbone
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from migen.bank.description import *
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from misoclib.soc import SoC
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from misoclib.tools.litescope.common import *
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from misoclib.tools.litescope.bridge.uart2wb import LiteScopeUART2WB
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from misoclib.tools.litescope.frontend.la import LiteScopeLA
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from misoclib.tools.litescope.core.port import LiteScopeTerm
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from misoclib.com.liteeth.common import *
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from misoclib.com.liteeth.generic import *
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from misoclib.com.liteeth.phy.gmii import LiteEthPHYGMII
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from misoclib.com.liteeth.core import LiteEthUDPIPCore
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class _CRG(Module):
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def __init__(self, clk_in):
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_por = ClockDomain(reset_less=True)
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# Power on Reset (vendor agnostic)
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rst_n = Signal()
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self.sync.por += rst_n.eq(1)
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self.comb += [
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self.cd_sys.clk.eq(clk_in),
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self.cd_por.clk.eq(clk_in),
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self.cd_sys.rst.eq(~rst_n)
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]
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class BaseSoC(SoC, AutoCSR):
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csr_map = {
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"phy": 11,
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"core": 12
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}
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csr_map.update(SoC.csr_map)
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def __init__(self, platform, clk_freq=166*1000000,
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mac_address=0x10e2d5000000,
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ip_address="192.168.1.40"):
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clk_freq = int((1/(platform.default_clk_period))*1000000000)
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self.submodules.uart2wb = LiteScopeUART2WB(platform.request("serial"), clk_freq, baudrate=115200)
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SoC.__init__(self, platform, clk_freq, self.uart2wb,
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with_cpu=False,
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with_csr=True, csr_data_width=32,
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with_uart=False,
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with_identifier=True,
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with_timer=False
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)
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clk_in = platform.request(platform.default_clk_name)
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self.submodules.crg = _CRG(clk_in if not hasattr(clk_in, "p") else clk_in.p)
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# wishbone SRAM (to test Wishbone over UART and Etherbone)
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self.submodules.sram = wishbone.SRAM(1024)
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self.add_wb_slave(lambda a: a[23:25] == 1, self.sram.bus)
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# ethernet PHY and UDP/IP stack
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self.submodules.phy = LiteEthPHYGMII(platform.request("eth_clocks"), platform.request("eth"))
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self.submodules.core = LiteEthUDPIPCore(self.phy, mac_address, convert_ip(ip_address), clk_freq)
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class BaseSoCDevel(BaseSoC, AutoCSR):
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csr_map = {
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"la": 20
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}
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csr_map.update(BaseSoC.csr_map)
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def __init__(self, platform):
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BaseSoC.__init__(self, platform)
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self.core_icmp_rx_fsm_state = Signal(4)
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self.core_icmp_tx_fsm_state = Signal(4)
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self.core_udp_rx_fsm_state = Signal(4)
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self.core_udp_tx_fsm_state = Signal(4)
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self.core_ip_rx_fsm_state = Signal(4)
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self.core_ip_tx_fsm_state = Signal(4)
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self.core_arp_rx_fsm_state = Signal(4)
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self.core_arp_tx_fsm_state = Signal(4)
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self.core_arp_table_fsm_state = Signal(4)
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debug = (
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# MAC interface
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self.core.mac.core.sink.stb,
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self.core.mac.core.sink.sop,
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self.core.mac.core.sink.eop,
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self.core.mac.core.sink.ack,
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self.core.mac.core.sink.data,
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self.core.mac.core.source.stb,
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self.core.mac.core.source.sop,
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self.core.mac.core.source.eop,
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self.core.mac.core.source.ack,
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self.core.mac.core.source.data,
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# ICMP interface
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self.core.icmp.echo.sink.stb,
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self.core.icmp.echo.sink.sop,
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self.core.icmp.echo.sink.eop,
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self.core.icmp.echo.sink.ack,
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self.core.icmp.echo.sink.data,
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self.core.icmp.echo.source.stb,
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self.core.icmp.echo.source.sop,
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self.core.icmp.echo.source.eop,
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self.core.icmp.echo.source.ack,
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self.core.icmp.echo.source.data,
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# IP interface
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self.core.ip.crossbar.master.sink.stb,
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self.core.ip.crossbar.master.sink.sop,
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self.core.ip.crossbar.master.sink.eop,
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self.core.ip.crossbar.master.sink.ack,
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self.core.ip.crossbar.master.sink.data,
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self.core.ip.crossbar.master.sink.ip_address,
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self.core.ip.crossbar.master.sink.protocol,
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# State machines
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self.core_icmp_rx_fsm_state,
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self.core_icmp_tx_fsm_state,
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self.core_arp_rx_fsm_state,
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self.core_arp_tx_fsm_state,
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self.core_arp_table_fsm_state,
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self.core_ip_rx_fsm_state,
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self.core_ip_tx_fsm_state,
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self.core_udp_rx_fsm_state,
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self.core_udp_tx_fsm_state
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)
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self.submodules.la = LiteScopeLA(debug, 4096)
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self.la.trigger.add_port(LiteScopeTerm(self.la.dw))
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def do_finalize(self):
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BaseSoC.do_finalize(self)
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self.comb += [
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self.core_icmp_rx_fsm_state.eq(self.core.icmp.rx.fsm.state),
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self.core_icmp_tx_fsm_state.eq(self.core.icmp.tx.fsm.state),
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self.core_arp_rx_fsm_state.eq(self.core.arp.rx.fsm.state),
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self.core_arp_tx_fsm_state.eq(self.core.arp.tx.fsm.state),
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self.core_arp_table_fsm_state.eq(self.core.arp.table.fsm.state),
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self.core_ip_rx_fsm_state.eq(self.core.ip.rx.fsm.state),
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self.core_ip_tx_fsm_state.eq(self.core.ip.tx.fsm.state),
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self.core_udp_rx_fsm_state.eq(self.core.udp.rx.fsm.state),
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self.core_udp_tx_fsm_state.eq(self.core.udp.tx.fsm.state)
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]
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def do_exit(self, vns):
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self.la.export(vns, "test/la.csv")
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default_subtarget = BaseSoC
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