enjoy-digital a8c48b42f9 Merge pull request #1281 from antmicro/i2s_f4pga_fix ... Add LiteX equivalent of Xilinx FIFO_SYNC_MACRO to I2S		2022-05-06 09:10:22 +02:00
..
build	xilinx/vivado: Differentiate IOs and internal nets when applying timing constraints.	2022-04-21 18:15:05 +02:00
compat	cores/spi_flash: Deprecate SPI Flash MMAPed cores (Designs have been switched with LiteSPI).	2022-01-07 19:08:03 +01:00
gen	xilinx/vivado: Differentiate IOs and internal nets when applying timing constraints.	2022-04-21 18:15:05 +02:00
soc	Merge pull request #1281 from antmicro/i2s_f4pga_fix	2022-05-06 09:10:22 +02:00
tools	tools: Add initial LiteX standalone SoC generator.	2022-05-05 17:36:34 +02:00
__init__.py	get_data_mod: Update pip to pip3 to avoid issues on systems with Python2 still installed.	2021-09-28 16:27:13 +02:00