Florent Kermarrec 8d1c555e36 misoclib/com/uart: remove irq condition parameters and use "non-full" for tx irq, "non-empty" for rx irq. ... An optimal solution for both sync and async mode is not easy to implement, it would requires moving CDC out of UART module and handling in the PHY with AsyncFIFO or minimal depth. For now use the solution that works for both cases. We'll try to optimize that if we have performance issues.		2015-07-25 00:25:09 +02:00
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com	misoclib/com/uart: remove irq condition parameters and use "non-full" for tx irq, "non-empty" for rx irq.	2015-07-25 00:25:09 +02:00
cpu	misoclib/cpu: merge git.py in identifier	2015-05-02 18:42:33 +02:00
mem	wishbone2lasmi: fix "READ_DATA" state	2015-07-09 10:40:32 +02:00
soc	soc: support constants without value	2015-06-28 21:35:37 +02:00
tools	cores: replace Timeout with new WaitTimer	2015-05-12 16:14:38 +02:00
video	misoclib/video/dvisampler: add fifo_depth parameter	2015-07-13 11:03:33 +02:00
__init__.py	…
mxcrg.v	misoclib: integrate mxcrg.py in mlabs_video target, remove others directory	2015-07-24 23:16:45 +02:00