Florent Kermarrec a99aa9c7fd uart: rename wishbone to bridge		2015-05-09 16:24:28 +02:00
..
com	uart: rename wishbone to bridge	2015-05-09 16:24:28 +02:00
cpu	misoclib/cpu: merge git.py in identifier	2015-05-02 18:42:33 +02:00
mem	uart: rename wishbone to bridge	2015-05-09 16:24:28 +02:00
others	cores: avoid having too much directories when possible (for simple cores or cores contained in a single file)	2015-05-02 16:22:33 +02:00
soc	soc/sdram: Vivado 2015.1 still does not fix issue with L2 cache, update comment...	2015-05-04 12:28:49 +02:00
tools	uart: rename wishbone to bridge	2015-05-09 16:24:28 +02:00
video	global: more pep8	2015-04-13 18:02:26 +02:00
__init__.py	rename milkymist-ng to MiSoC	2013-11-09 15:27:32 +01:00