34 lines
1.3 KiB
Python
34 lines
1.3 KiB
Python
from migen.fhdl.structure import *
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from migen.fhdl.module import Module
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from migen.bank.description import *
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class ASMIprobe(Module):
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def __init__(self, hub, trace_depth=16):
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slots = hub.get_slots()
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slot_count = len(slots)
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assert(trace_depth < 256)
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assert(slot_count < 256)
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self._slot_count = RegisterField("slot_count", 8, access_bus=READ_ONLY, access_dev=WRITE_ONLY)
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self._trace_depth = RegisterField("trace_depth", 8, access_bus=READ_ONLY, access_dev=WRITE_ONLY)
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self._slot_status = [RegisterField("slot_status" + str(i), 2, access_bus=READ_ONLY, access_dev=WRITE_ONLY)
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for i in range(slot_count)]
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self._trace = [RegisterField("trace" + str(i), 8, access_bus=READ_ONLY, access_dev=WRITE_ONLY)
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for i in range(trace_depth)]
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###
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self.comb += [
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self._slot_count.field.w.eq(slot_count),
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self._trace_depth.field.w.eq(trace_depth)
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]
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for slot, status in zip(slots, self._slot_status):
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self.comb += status.field.w.eq(slot.state)
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shift_tags = [self._trace[n].field.w.eq(self._trace[n+1].field.w)
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for n in range(len(self._trace) - 1)]
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shift_tags.append(self._trace[-1].field.w.eq(hub.tag_call))
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self.sync += If(hub.call, *shift_tags)
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def get_registers(self):
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return [self._slot_count, self._trace_depth] + self._slot_status + self._trace
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