147 lines
5.1 KiB
Python
147 lines
5.1 KiB
Python
#
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# This file is part of LiteX.
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#
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# Copyright (c) 2019 Florent Kermarrec <florent@enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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import unittest
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from migen import *
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from litex.soc.interconnect import csr
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from litex.soc.interconnect import csr_bus
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def csr32_write(dut, adr, dat):
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for i in range(4):
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yield from dut.csr.write(adr + 3 - i, (dat >> 8*i) & 0xff)
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def csr32_read(dut, adr):
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dat = 0
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for i in range(5):
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dat |= ((yield from dut.csr.read(adr + 3 - i)) << 8*i)
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return dat >> 8
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class CSRModule(Module, csr.AutoCSR):
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def __init__(self):
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self._csr = csr.CSR()
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self._constant = csr.CSRConstant(0x12345678)
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self._storage = csr.CSRStorage(32, reset=0x12345678, write_from_dev=True)
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self._status = csr.CSRStatus(32, reset=0x12345678)
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# # #
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# When csr is written:
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# - Set storage to 0xdeadbeef.
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# - Set status to storage value.
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self.comb += [
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If(self._csr.re,
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self._storage.we.eq(1),
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self._storage.dat_w.eq(0xdeadbeef)
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)
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]
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self.sync += [
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If(self._csr.re,
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self._status.status.eq(self._storage.storage)
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)
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]
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class CSRDUT(Module):
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def address_map(self, name, memory):
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return {"csrmodule": 0}[name]
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def __init__(self):
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self.csr = csr_bus.Interface()
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self.submodules.csrmodule = CSRModule()
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self.submodules.csrbankarray = csr_bus.CSRBankArray(
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source = self,
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address_map = self.address_map,
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)
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self.submodules.csrcon = csr_bus.Interconnect(
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master = self.csr,
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slaves = self.csrbankarray.get_buses()
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)
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class TestCSR(unittest.TestCase):
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def test_csr_constant(self):
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def generator(dut):
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self.assertEqual(hex((yield from dut.csrmodule._constant.read())), hex(0x12345678))
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dut = CSRDUT()
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run_simulation(dut, generator(dut))
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def test_csr_storage(self):
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def generator(dut):
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# check init value
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self.assertEqual(hex((yield from csr32_read(dut, 5))), hex(0x12345678))
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# check writes
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yield from csr32_write(dut, 1, 0x5a5a5a5a)
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self.assertEqual(hex((yield from csr32_read(dut, 1))), hex(0x5a5a5a5a))
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yield from csr32_write(dut, 1, 0xa5a5a5a5)
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self.assertEqual(hex((yield from csr32_read(dut, 1))), hex(0xa5a5a5a5))
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# check update from dev
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yield from dut.csr.write(0, 1)
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self.assertEqual(hex((yield from csr32_read(dut, 1))), hex(0xdeadbeef))
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dut = CSRDUT()
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run_simulation(dut, generator(dut))
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def test_csr_status(self):
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def generator(dut):
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# check init value
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self.assertEqual(hex((yield from csr32_read(dut, 1))), hex(0x12345678))
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# check writes (no effect)
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yield from csr32_write(dut, 5, 0x5a5a5a5a)
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self.assertEqual(hex((yield from csr32_read(dut, 5))), hex(0x12345678))
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yield from csr32_write(dut, 5, 0xa5a5a5a5)
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self.assertEqual(hex((yield from csr32_read(dut, 5))), hex(0x12345678))
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# check update from dev
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yield from dut.csr.write(0, 1)
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yield from dut.csr.write(0, 1)
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self.assertEqual(hex((yield from csr32_read(dut, 5))), hex(0xdeadbeef))
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dut = CSRDUT()
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run_simulation(dut, generator(dut))
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def test_csr_fields(self):
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def generator(dut):
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# check reset values
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self.assertEqual((yield dut._storage.fields.foo), 0xa)
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self.assertEqual((yield dut._storage.fields.bar), 0x5a)
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self.assertEqual((yield dut._storage.storage), 0x5a000a)
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self.assertEqual((yield from dut._storage.read()), 0x5a000a)
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yield
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yield
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self.assertEqual((yield dut._status.fields.foo), 0xa)
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self.assertEqual((yield dut._status.fields.bar), 0x5a)
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try:
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self.assertEqual((yield dut._status.status), 0x5a000a)
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self.assertEqual((yield from dut._status.read()), 0x5a000a)
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except self.failureException as exc:
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print("Skipping:" + repr(exc))
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raise self.skipTest("skip known failure") from None
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class DUT(Module):
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def __init__(self):
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self._storage = csr.CSRStorage(fields=[
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csr.CSRField("foo", size=4, offset=0, reset=0xa, description="foo"),
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csr.CSRField("bar", size=8, offset=16, reset=0x5a, description="bar")
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])
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self._status = csr.CSRStatus(fields=[
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csr.CSRField("foo", size=4, offset=4, description="foo"),
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csr.CSRField("bar", size=8, offset=8, description="bar")
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])
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self.comb += [
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self._status.fields.foo.eq(self._storage.fields.foo),
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self._status.fields.bar.eq(self._storage.fields.bar),
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]
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dut = DUT()
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run_simulation(dut, generator(dut))
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