206 lines
6.2 KiB
Python
206 lines
6.2 KiB
Python
from migen.fhdl.structure import *
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from migen.corelogic import roundrobin
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from migen.corelogic.misc import multimux, optree
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from migen.bus.simple import *
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from migen.bus.transactions import *
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_desc = Description(
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(M_TO_S, "adr", 30),
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(M_TO_S, "dat_w", 32),
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(S_TO_M, "dat_r", 32),
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(M_TO_S, "sel", 4),
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(M_TO_S, "cyc", 1),
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(M_TO_S, "stb", 1),
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(S_TO_M, "ack", 1),
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(M_TO_S, "we", 1),
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(M_TO_S, "cti", 3),
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(M_TO_S, "bte", 2),
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(S_TO_M, "err", 1)
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)
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class Interface(SimpleInterface):
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def __init__(self):
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SimpleInterface.__init__(self, _desc)
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class InterconnectPointToPoint(SimpleInterconnect):
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def __init__(self, master, slave):
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SimpleInterconnect.__init__(self, master, [slave])
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class Arbiter:
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def __init__(self, masters, target):
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self.masters = masters
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self.target = target
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self.rr = roundrobin.RoundRobin(len(self.masters))
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def get_fragment(self):
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comb = []
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# mux master->slave signals
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m2s_names = _desc.get_names(M_TO_S)
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m2s_masters = [[getattr(m, name) for name in m2s_names] for m in self.masters]
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m2s_target = [getattr(self.target, name) for name in m2s_names]
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comb += multimux(self.rr.grant, m2s_masters, m2s_target)
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# connect slave->master signals
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for name in _desc.get_names(S_TO_M):
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source = getattr(self.target, name)
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for i, m in enumerate(self.masters):
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dest = getattr(m, name)
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if name == "ack" or name == "err":
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comb.append(dest.eq(source & (self.rr.grant == Constant(i, self.rr.grant.bv))))
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else:
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comb.append(dest.eq(source))
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# connect bus requests to round-robin selector
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reqs = [m.cyc for m in self.masters]
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comb.append(self.rr.request.eq(Cat(*reqs)))
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return Fragment(comb) + self.rr.get_fragment()
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class Decoder:
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# slaves is a list of pairs:
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# 0) structure.Constant defining address (always decoded on the upper bits)
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# Slaves can have differing numbers of address bits, but addresses
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# must not conflict.
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# 1) wishbone.Slave reference
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# Addresses are decoded from bit 31-offset and downwards.
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# register adds flip-flops after the address comparators. Improves timing,
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# but breaks Wishbone combinatorial feedback.
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def __init__(self, master, slaves, offset=0, register=False):
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self.master = master
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self.slaves = slaves
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self.offset = offset
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self.register = register
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addresses = [slave[0] for slave in self.slaves]
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maxbits = max([bits_for(addr) for addr in addresses])
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def mkconst(x):
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if isinstance(x, int):
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return Constant(x, BV(maxbits))
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else:
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return x
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self.addresses = list(map(mkconst, addresses))
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def get_fragment(self):
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comb = []
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sync = []
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ns = len(self.slaves)
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slave_sel = Signal(BV(ns))
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slave_sel_r = Signal(BV(ns))
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# decode slave addresses
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hi = self.master.adr.bv.width - self.offset
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comb += [slave_sel[i].eq(self.master.adr[hi-addr.bv.width:hi] == addr)
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for i, addr in enumerate(self.addresses)]
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if self.register:
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sync.append(slave_sel_r.eq(slave_sel))
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else:
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comb.append(slave_sel_r.eq(slave_sel))
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# connect master->slaves signals except cyc
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m2s_names = _desc.get_names(M_TO_S, "cyc")
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comb += [getattr(slave[1], name).eq(getattr(self.master, name))
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for name in m2s_names for slave in self.slaves]
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# combine cyc with slave selection signals
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comb += [slave[1].cyc.eq(self.master.cyc & slave_sel[i])
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for i, slave in enumerate(self.slaves)]
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# generate master ack (resp. err) by ORing all slave acks (resp. errs)
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comb += [
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self.master.ack.eq(optree("|", [slave[1].ack for slave in self.slaves])),
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self.master.err.eq(optree("|", [slave[1].err for slave in self.slaves]))
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]
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# mux (1-hot) slave data return
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masked = [Replicate(slave_sel_r[i], self.master.dat_r.bv.width) & self.slaves[i][1].dat_r for i in range(len(self.slaves))]
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comb.append(self.master.dat_r.eq(optree("|", masked)))
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return Fragment(comb, sync)
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class InterconnectShared:
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def __init__(self, masters, slaves, offset=0, register=False):
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self._shared = Interface()
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self._arbiter = Arbiter(masters, self._shared)
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self._decoder = Decoder(self._shared, slaves, offset, register)
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self.addresses = self._decoder.addresses
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def get_fragment(self):
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return self._arbiter.get_fragment() + self._decoder.get_fragment()
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class Tap:
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def __init__(self, bus=None, handler=print):
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# If bus is None, create one and act as a normal slave.
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# If we pass an existing one, dump the transactions
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# without interfering with the bus.
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if bus is None:
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self.bus = Interface()
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self.ack = True
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else:
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self.bus = bus
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self.ack = False
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self.handler = handler
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def do_simulation(self, s):
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if s.rd(self.bus.ack):
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assert(s.rd(self.bus.cyc) and s.rd(self.bus.stb))
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if s.rd(self.bus.we):
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transaction = TWrite(s.rd(self.bus.adr),
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s.rd(self.bus.dat_w),
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s.rd(self.bus.sel))
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else:
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transaction = TRead(s.rd(self.bus.adr),
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s.rd(self.bus.dat_r))
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self.handler(transaction)
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def get_fragment(self):
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if self.ack:
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sync = [
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self.bus.ack.eq(0),
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If(self.bus.cyc & self.bus.stb & ~self.bus.ack,
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self.bus.ack.eq(1)
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)
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]
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else:
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sync = []
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return Fragment(sync=sync, sim=[self.do_simulation])
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class Initiator:
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def __init__(self, generator):
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self.generator = generator
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self.bus = Interface()
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self.transaction_start = 0
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self.transaction = None
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self.done = False
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def do_simulation(self, s):
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if not self.done:
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if self.transaction is None or s.rd(self.bus.ack):
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if self.transaction is not None:
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self.transaction.latency = s.cycle_counter - self.transaction_start - 1
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if isinstance(self.transaction, TRead):
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self.transaction.data = s.rd(self.bus.dat_r)
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try:
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self.transaction = next(self.generator)
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except StopIteration:
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self.done = True
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self.transaction = None
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if self.transaction is not None:
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self.transaction_start = s.cycle_counter
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s.wr(self.bus.cyc, 1)
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s.wr(self.bus.stb, 1)
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s.wr(self.bus.adr, self.transaction.address)
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if isinstance(self.transaction, TWrite):
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s.wr(self.bus.we, 1)
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s.wr(self.bus.sel, self.transaction.sel)
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s.wr(self.bus.dat_w, self.transaction.data)
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else:
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s.wr(self.bus.we, 0)
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else:
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s.wr(self.bus.cyc, 0)
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s.wr(self.bus.stb, 0)
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def get_fragment(self):
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return Fragment(sim=[self.do_simulation])
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