206 lines
4.9 KiB
Python
206 lines
4.9 KiB
Python
from migen.fhdl.std import *
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from migen.genlib.cdc import MultiReg, PulseSynchronizer
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from migen.genlib.fifo import AsyncFIFO
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from migen.genlib.record import Record
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from migen.bank.description import *
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from migen.flow.actor import *
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from misoclib.dvisampler.common import channel_layout
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class SyncPolarity(Module):
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def __init__(self):
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self.valid_i = Signal()
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self.data_in0 = Record(channel_layout)
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self.data_in1 = Record(channel_layout)
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self.data_in2 = Record(channel_layout)
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self.valid_o = Signal()
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self.de = Signal()
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self.hsync = Signal()
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self.vsync = Signal()
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self.r = Signal(8)
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self.g = Signal(8)
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self.b = Signal(8)
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###
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de = self.data_in0.de
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de_r = Signal()
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c = self.data_in0.c
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c_polarity = Signal(2)
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c_out = Signal(2)
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self.comb += [
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self.de.eq(de_r),
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self.hsync.eq(c_out[0]),
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self.vsync.eq(c_out[1])
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]
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self.sync.pix += [
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self.valid_o.eq(self.valid_i),
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self.r.eq(self.data_in2.d),
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self.g.eq(self.data_in1.d),
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self.b.eq(self.data_in0.d),
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de_r.eq(de),
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If(de_r & ~de,
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c_polarity.eq(c),
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c_out.eq(0)
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).Else(
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c_out.eq(c ^ c_polarity)
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)
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]
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class ResolutionDetection(Module, AutoCSR):
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def __init__(self, nbits=11):
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self.valid_i = Signal()
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self.vsync = Signal()
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self.de = Signal()
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self._hres = CSRStatus(nbits)
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self._vres = CSRStatus(nbits)
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###
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# Detect DE transitions
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de_r = Signal()
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pn_de = Signal()
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self.sync.pix += de_r.eq(self.de)
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self.comb += pn_de.eq(~self.de & de_r)
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# HRES
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hcounter = Signal(nbits)
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self.sync.pix += If(self.valid_i & self.de,
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hcounter.eq(hcounter + 1)
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).Else(
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hcounter.eq(0)
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)
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hcounter_st = Signal(nbits)
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self.sync.pix += If(self.valid_i,
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If(pn_de, hcounter_st.eq(hcounter))
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).Else(
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hcounter_st.eq(0)
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)
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self.specials += MultiReg(hcounter_st, self._hres.status)
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# VRES
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vsync_r = Signal()
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p_vsync = Signal()
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self.sync.pix += vsync_r.eq(self.vsync),
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self.comb += p_vsync.eq(self.vsync & ~vsync_r)
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vcounter = Signal(nbits)
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self.sync.pix += If(self.valid_i & p_vsync,
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vcounter.eq(0)
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).Elif(pn_de,
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vcounter.eq(vcounter + 1)
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)
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vcounter_st = Signal(nbits)
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self.sync.pix += If(self.valid_i,
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If(p_vsync, vcounter_st.eq(vcounter))
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).Else(
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vcounter_st.eq(0)
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)
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self.specials += MultiReg(vcounter_st, self._vres.status)
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class FrameExtraction(Module, AutoCSR):
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def __init__(self, word_width):
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# in pix clock domain
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self.valid_i = Signal()
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self.vsync = Signal()
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self.de = Signal()
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self.r = Signal(8)
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self.g = Signal(8)
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self.b = Signal(8)
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# in sys clock domain
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word_layout = [("sof", 1), ("pixels", word_width)]
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self.frame = Source(word_layout)
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self.busy = Signal()
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self._r_overflow = CSR()
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###
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# start of frame detection
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vsync_r = Signal()
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new_frame = Signal()
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self.comb += new_frame.eq(self.vsync & ~vsync_r)
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self.sync.pix += vsync_r.eq(self.vsync)
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# pack pixels into words
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cur_word = Signal(word_width)
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cur_word_valid = Signal()
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encoded_pixel = Signal(24)
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self.comb += encoded_pixel.eq(Cat(self.b, self.g, self.r))
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pack_factor = word_width//24
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assert(pack_factor & (pack_factor - 1) == 0) # only support powers of 2
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pack_counter = Signal(max=pack_factor)
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self.sync.pix += [
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cur_word_valid.eq(0),
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If(new_frame,
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cur_word_valid.eq(pack_counter == (pack_factor - 1)),
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pack_counter.eq(0),
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).Elif(self.valid_i & self.de,
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[If(pack_counter == (pack_factor-i-1),
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cur_word[24*i:24*(i+1)].eq(encoded_pixel)) for i in range(pack_factor)],
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cur_word_valid.eq(pack_counter == (pack_factor - 1)),
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pack_counter.eq(pack_counter + 1)
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)
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]
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# FIFO
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fifo = RenameClockDomains(AsyncFIFO(word_layout, 512),
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{"write": "pix", "read": "sys"})
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self.submodules += fifo
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self.comb += [
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fifo.din.pixels.eq(cur_word),
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fifo.we.eq(cur_word_valid)
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]
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self.sync.pix += \
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If(new_frame,
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fifo.din.sof.eq(1)
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).Elif(cur_word_valid,
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fifo.din.sof.eq(0)
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)
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self.comb += [
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self.frame.stb.eq(fifo.readable),
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self.frame.payload.eq(fifo.dout),
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fifo.re.eq(self.frame.ack),
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self.busy.eq(0)
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]
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# overflow detection
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pix_overflow = Signal()
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pix_overflow_reset = Signal()
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self.sync.pix += [
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If(fifo.we & ~fifo.writable,
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pix_overflow.eq(1)
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).Elif(pix_overflow_reset,
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pix_overflow.eq(0)
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)
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]
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sys_overflow = Signal()
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self.specials += MultiReg(pix_overflow, sys_overflow)
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self.submodules.overflow_reset = PulseSynchronizer("sys", "pix")
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self.submodules.overflow_reset_ack = PulseSynchronizer("pix", "sys")
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self.comb += [
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pix_overflow_reset.eq(self.overflow_reset.o),
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self.overflow_reset_ack.i.eq(pix_overflow_reset)
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]
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overflow_mask = Signal()
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self.comb += [
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self._r_overflow.w.eq(sys_overflow & ~overflow_mask),
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self.overflow_reset.i.eq(self._r_overflow.re)
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]
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self.sync += \
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If(self._r_overflow.re,
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overflow_mask.eq(1)
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).Elif(self.overflow_reset_ack.o,
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overflow_mask.eq(0)
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)
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