131 lines
4.2 KiB
Python
131 lines
4.2 KiB
Python
#
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# This file is part of MiSoC and has been adapted/modified for Litex.
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#
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# Copyright 2007-2023 / M-Labs Ltd
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# Copyright 2012-2015 / Enjoy-Digital
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# Copyright from Misoc LICENCE file added above
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#
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# Copyright 2023 Andrew Dennison <andrew@motec.com.au>
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#
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# SPDX-License-Identifier: BSD-2-Clause
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import unittest
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from migen import *
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from migen.fhdl.specials import Tristate
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from litex.soc.cores.i2c import *
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class _MockPads:
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def __init__(self):
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self.scl = Signal()
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self.sda = Signal()
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class _MockTristateImpl(Module):
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def __init__(self, t):
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oe = Signal()
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self.comb += [
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t.target.eq(t.o),
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oe.eq(t.oe),
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]
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class _MockTristate:
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@staticmethod
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def lower(t):
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return _MockTristateImpl(t)
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class TestI2C(unittest.TestCase):
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def test_i2c(self):
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pads = _MockPads()
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dut = I2CMaster(pads)
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def check_trans(scl, sda):
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scl_init, sda_init = (yield dut.i2c.scl_o), (yield dut.i2c.sda_o)
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timeout = 0
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while True:
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timeout += 1
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self.assertLess(timeout, 20)
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scl_now, sda_now = (yield dut.i2c.scl_o), (yield dut.i2c.sda_o)
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if scl_now != scl_init or sda_now != sda_init:
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self.assertEqual(scl_now, scl)
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self.assertEqual(sda_now, sda)
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return
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yield
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def wait_idle(do=lambda: ()):
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timeout = 0
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while True:
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timeout += 1
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self.assertLess(timeout, 20)
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idle = ((yield from dut.bus.read(I2C_XFER_ADDR)) & I2C_IDLE) != 0
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if idle:
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return
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yield
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def write_bit(value):
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yield from check_trans(scl=False, sda=value)
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yield from check_trans(scl=True, sda=value)
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def write_ack(value):
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yield from check_trans(scl=False, sda=not value)
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yield from check_trans(scl=True, sda=not value)
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yield from wait_idle()
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def read_bit(value):
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yield from check_trans(scl=False, sda=True)
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yield dut.sda_t.i.eq(value)
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yield from check_trans(scl=True, sda=True)
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def read_ack(value):
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yield from check_trans(scl=False, sda=True)
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yield dut.sda_t.i.eq(not value)
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yield from check_trans(scl=True, sda=True)
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yield from wait_idle()
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ack = ((yield from dut.bus.read(I2C_XFER_ADDR)) & I2C_ACK) != 0
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self.assertEqual(ack, value)
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def check():
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yield from dut.bus.write(I2C_CONFIG_ADDR, 4)
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yield from dut.bus.write(I2C_XFER_ADDR, I2C_START)
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yield from check_trans(scl=True, sda=False)
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yield from wait_idle()
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yield from dut.bus.write(I2C_XFER_ADDR, I2C_WRITE | 0x82)
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for i in [True, False, False, False, False, False, True, False]:
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yield from write_bit(i)
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yield from read_ack(True)
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yield from dut.bus.write(I2C_XFER_ADDR, I2C_WRITE | 0x18)
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for i in [False, False, False, True, True, False, False, False]:
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yield from write_bit(i)
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yield from read_ack(False)
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yield from dut.bus.write(I2C_XFER_ADDR, I2C_START | I2C_STOP)
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yield from check_trans(scl=True, sda=False)
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yield from wait_idle()
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yield from dut.bus.write(I2C_XFER_ADDR, I2C_READ)
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for i in [False, False, False, True, True, False, False, False]:
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yield from read_bit(i)
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data = (yield from dut.bus.read(I2C_XFER_ADDR)) & 0xff
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self.assertEqual(data, 0x18)
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yield from write_ack(False)
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yield from dut.bus.write(I2C_XFER_ADDR, I2C_READ | I2C_ACK)
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for i in [True, False, False, False, True, False, False, False]:
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yield from read_bit(i)
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data = (yield dut.i2c.data)
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self.assertEqual(data, 0x88)
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yield from write_ack(True)
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yield from dut.bus.write(I2C_XFER_ADDR, I2C_STOP)
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yield from check_trans(scl=False, sda=False)
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yield from wait_idle()
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run_simulation(dut, check(), special_overrides={Tristate: _MockTristate}, vcd_name="i2c.vcd")
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