120 lines
4.1 KiB
Python
120 lines
4.1 KiB
Python
from mibuild.generic_platform import *
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from mibuild.xilinx_ise import XilinxISEPlatform, CRG_SE
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_io = [
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("user_btn", 0, Pins("V4"), IOStandard("LVCMOS33"),
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Misc("PULLDOWN"), Misc("TIG")),
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("user_led", 0, Pins("P4"), Misc("SLEW=QUIETIO"), IOStandard("LVCMOS18")),
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("user_led", 1, Pins("L6"), Misc("SLEW=QUIETIO"), IOStandard("LVCMOS18")),
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("user_led", 2, Pins("F5"), Misc("SLEW=QUIETIO"), IOStandard("LVCMOS18")),
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("user_led", 3, Pins("C2"), Misc("SLEW=QUIETIO"), IOStandard("LVCMOS18")),
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("user_dip", 0, Pins("B3"), Misc("PULLDOWN"), IOStandard("LVCMOS33")),
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("user_dip", 1, Pins("A3"), Misc("PULLDOWN"), IOStandard("LVCMOS33")),
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("user_dip", 2, Pins("B4"), Misc("PULLDOWN"), IOStandard("LVCMOS33")),
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("user_dip", 3, Pins("A4"), Misc("PULLDOWN"), IOStandard("LVCMOS33")),
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# TI CDCE913 programmable triple-output PLL
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("clk_y1", 0, Pins("V10"), IOStandard("LVCMOS33")), # default: 40 MHz
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("clk_y2", 0, Pins("K15"), IOStandard("LVCMOS33")), # default: 66 2/3 MHz
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("clk_y3", 0, Pins("C10"), IOStandard("LVCMOS33")), # default: 100 MHz
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# Maxim DS1088LU oscillator, not populated
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("clk_backup", 0, Pins("R8"), IOStandard("LVCMOS33")),
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# TI CDCE913 PLL I2C control
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("pll", 0,
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Subsignal("scl", Pins("P12")),
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Subsignal("sda", Pins("U13")),
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Misc("PULLUP"),
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IOStandard("LVCMOS33")),
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# Micron N25Q128 SPI Flash
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("spiflash", 0,
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Subsignal("clk", Pins("R15")),
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Subsignal("cs_n", Pins("V3")),
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Subsignal("dq", Pins("T13 R13 T14 V14")),
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IOStandard("LVCMOS33")),
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# PMOD extension connectors
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("pmod", 0,
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Subsignal("d", Pins("F15 F16 C17 C18 F14 G14 D17 D18")),
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IOStandard("LVCMOS33")),
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("pmod", 1,
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Subsignal("d", Pins("H12 G13 E16 E18 K12 K13 F17 F18")),
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IOStandard("LVCMOS33")),
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("serial", 0,
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Subsignal("tx", Pins("T7"), Misc("SLEW=SLOW")),
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Subsignal("rx", Pins("R7"), Misc("PULLUP")),
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IOStandard("LVCMOS33")),
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("ddram_clock", 0,
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Subsignal("p", Pins("G3")),
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Subsignal("n", Pins("G1")),
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IOStandard("MOBILE_DDR")), # actually DIFF_
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# Micron MT46H32M16LFBF-5 LPDDR
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("ddram", 0,
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Subsignal("a", Pins("J7 J6 H5 L7 F3 H4 H3 H6 "
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"D2 D1 F4 D3 G6")),
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Subsignal("ba", Pins("F2 F1")),
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Subsignal("dq", Pins("L2 L1 K2 K1 H2 H1 J3 J1 "
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"M3 M1 N2 N1 T2 T1 U2 U1")),
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Subsignal("cke", Pins("H7")),
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Subsignal("we_n", Pins("E3")),
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Subsignal("cs_n", Pins("K6")), # NC!
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Subsignal("cas_n", Pins("K5")),
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Subsignal("ras_n", Pins("L5")),
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Subsignal("dm", Pins("K3", "K4")),
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Subsignal("dqs", Pins("L4", "P2")),
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Subsignal("rzq", Pins("N4")),
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IOStandard("MOBILE_DDR")),
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# Nat Semi DP83848J 10/100 Ethernet PHY
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# pull-ups on rx_data set phy addr to 11110b
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# and prevent isolate mode (addr 00000b)
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("eth_clocks", 0,
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Subsignal("rx", Pins("L15")),
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Subsignal("tx", Pins("H17")),
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IOStandard("LVCMOS33")),
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("eth", 0,
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Subsignal("col", Pins("M18"), Misc("PULLDOWN")),
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Subsignal("crs", Pins("N17"), Misc("PULLDOWN")),
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Subsignal("mdc", Pins("M16")),
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Subsignal("mdio", Pins("L18")),
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Subsignal("rst_n", Pins("T18"), Misc("TIG")),
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Subsignal("rx_data", Pins("T17 N16 N15 P18"), Misc("PULLUP")),
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Subsignal("dv", Pins("P17")),
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Subsignal("rx_er", Pins("N18")),
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Subsignal("tx_data", Pins("K18 K17 J18 J16")),
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Subsignal("tx_en", Pins("L17")),
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Subsignal("tx_er", Pins("L16")), # NC!
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IOStandard("LVCMOS33")),
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]
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class Platform(XilinxISEPlatform):
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def __init__(self):
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XilinxISEPlatform.__init__(self, "xc6slx9-2csg324", _io,
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lambda p: CRG_SE(p, "clk_y3", "user_btn", 10.))
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self.add_platform_command("""
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CONFIG VCCAUX = "3.3";
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""")
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def do_finalize(self, fragment):
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try:
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eth_clocks = self.lookup_request("eth_clocks")
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self.add_platform_command("""
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NET "{phy_rx_clk}" TNM_NET = "GRPphy_rx_clk";
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NET "{phy_tx_clk}" TNM_NET = "GRPphy_tx_clk";
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TIMESPEC "TSphy_rx_clk" = PERIOD "GRPphy_rx_clk" 40 ns HIGH 50%;
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TIMESPEC "TSphy_tx_clk" = PERIOD "GRPphy_tx_clk" 40 ns HIGH 50%;
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TIMESPEC "TSphy_tx_clk_io" = FROM "GRPphy_tx_clk" TO "PADS" 10 ns;
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TIMESPEC "TSphy_rx_clk_io" = FROM "PADS" TO "GRPphy_rx_clk" 10 ns;
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""", phy_rx_clk=eth_clocks.rx, phy_tx_clk=eth_clocks.tx)
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except ContraintError:
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pass
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