91 lines
2.5 KiB
Python
91 lines
2.5 KiB
Python
from operator import itemgetter
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from migen.fhdl.std import *
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from migen.bus import csr
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from migen.bank.description import *
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class Bank(Module):
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def __init__(self, description, address=0, bus=None):
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if bus is None:
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bus = csr.Interface()
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self.bus = bus
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###
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if not description:
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return
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# Turn description into simple CSRs and claim ownership of compound CSR modules
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simple_csrs = []
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for c in description:
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if isinstance(c, CSR):
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simple_csrs.append(c)
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else:
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c.finalize(csr.data_width)
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simple_csrs += c.get_simple_csrs()
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self.submodules += c
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nbits = bits_for(len(simple_csrs)-1)
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# Decode selection
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sel = Signal()
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self.comb += sel.eq(self.bus.adr[9:] == address)
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# Bus writes
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for i, c in enumerate(simple_csrs):
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self.comb += [
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c.r.eq(self.bus.dat_w[:c.size]),
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c.re.eq(sel & \
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self.bus.we & \
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(self.bus.adr[:nbits] == i))
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]
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# Bus reads
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brcases = dict((i, self.bus.dat_r.eq(c.w)) for i, c in enumerate(simple_csrs))
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self.sync += [
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self.bus.dat_r.eq(0),
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If(sel, Case(self.bus.adr[:nbits], brcases))
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]
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# address_map(name, memory) returns the CSR offset at which to map
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# the CSR object (register bank or memory).
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# If memory=None, the object is the register bank of object source.name.
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# Otherwise, it is a memory object belonging to source.name.
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# address_map is called exactly once for each object at each call to
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# scan(), so it can have side effects.
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class BankArray(Module):
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def __init__(self, source, address_map):
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self.source = source
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self.address_map = address_map
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self.scan()
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def scan(self):
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self.banks = []
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self.srams = []
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for name, obj in sorted(self.source.__dict__.items(), key=itemgetter(0)):
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if hasattr(obj, "get_csrs"):
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csrs = obj.get_csrs()
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else:
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csrs = []
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if hasattr(obj, "get_memories"):
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memories = obj.get_memories()
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for memory in memories:
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mapaddr = self.address_map(name, memory)
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mmap = csr.SRAM(memory, mapaddr)
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self.submodules += mmap
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csrs += mmap.get_csrs()
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self.srams.append((name, memory, mapaddr, mmap))
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if csrs:
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mapaddr = self.address_map(name, None)
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rmap = Bank(csrs, mapaddr)
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self.submodules += rmap
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self.banks.append((name, csrs, mapaddr, rmap))
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def get_rmaps(self):
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return [rmap for name, csrs, mapaddr, rmap in self.banks]
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def get_mmaps(self):
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return [mmap for name, memory, mapaddr, mmap in self.srams]
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def get_buses(self):
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return [i.bus for i in self.get_rmaps() + self.get_mmaps()]
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