259 lines
8.1 KiB
Python
259 lines
8.1 KiB
Python
from migen.fhdl.std import *
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from migen.bus.transactions import *
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from migen.genlib import roundrobin
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from migen.genlib.record import *
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from migen.genlib.misc import optree
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class Interface(Record):
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def __init__(self, aw, dw, nbanks, read_latency, write_latency):
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self.aw = aw
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self.dw = dw
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self.nbanks = nbanks
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self.read_latency = read_latency
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self.write_latency = write_latency
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bank_layout = [
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("adr", aw, DIR_M_TO_S),
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("we", 1, DIR_M_TO_S),
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("stb", 1, DIR_M_TO_S),
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("ack", 1, DIR_S_TO_M)
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]
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if nbanks > 1:
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layout = [("bank"+str(i), bank_layout) for i in range(nbanks)]
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else:
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layout = bank_layout
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layout += [
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("dat_w", dw, DIR_M_TO_S),
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("dat_we", dw//8, DIR_M_TO_S),
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("dat_r", dw, DIR_S_TO_M)
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]
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Record.__init__(self, layout)
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def _getattr_all(l, attr):
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it = iter(l)
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r = getattr(next(it), attr)
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for e in it:
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if getattr(e, attr) != r:
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raise ValueError
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return r
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class Crossbar(Module):
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def __init__(self, controllers, nmasters, cba_shift):
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ncontrollers = len(controllers)
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rca_bits = _getattr_all(controllers, "aw")
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dw = _getattr_all(controllers, "dw")
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nbanks = _getattr_all(controllers, "nbanks")
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read_latency = _getattr_all(controllers, "read_latency")
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write_latency = _getattr_all(controllers, "write_latency")
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bank_bits = log2_int(nbanks, False)
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controller_bits = log2_int(ncontrollers, False)
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self.masters = [Interface(rca_bits + bank_bits + controller_bits, dw, 1, read_latency, write_latency)
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for i in range(nmasters)]
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###
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m_ca, m_ba, m_rca = self._split_master_addresses(controller_bits, bank_bits, rca_bits, cba_shift)
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for nc, controller in enumerate(controllers):
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if controller_bits:
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controller_selected = [ca == nc for ca in m_ca]
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else:
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controller_selected = [1]*nmasters
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master_acks = [0]*nmasters
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for nb in range(nbanks):
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bank = getattr(controller, "bank"+str(nb))
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# arbitrate
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rr = roundrobin.RoundRobin(nmasters, roundrobin.SP_CE)
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self.submodules += rr
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bank_selected = [cs & (ba == nb) for cs, ba in zip(controller_selected, m_ba)]
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bank_requested = [bs & master.stb for bs, master in zip(bank_selected, self.masters)]
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self.comb += [
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rr.request.eq(Cat(*bank_requested)),
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rr.ce.eq(~bank.stb | bank.ack)
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]
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# route requests
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self.comb += [
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bank.adr.eq(Array(m_rca)[rr.grant]),
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bank.we.eq(Array(self.masters)[rr.grant].we),
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bank.stb.eq(Array(bank_requested)[rr.grant])
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]
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master_acks = [master_ack | ((rr.grant == nm) & bank.ack)
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for nm, master_ack in enumerate(master_acks)]
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self.comb += [master.ack.eq(master_ack) for master, master_ack in zip(self.masters, master_acks)]
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# route data writes
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controller_selected_wl = controller_selected
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for i in range(write_latency):
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n_controller_selected_wl = [Signal() for i in range(nmasters)]
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self.sync += [n.eq(o) for n, o in zip(n_controller_selected_wl, controller_selected_wl)]
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controller_selected_wl = n_controller_selected_wl
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dat_w_maskselect = []
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dat_we_maskselect = []
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for master, selected in zip(self.masters, controller_selected_wl):
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o_dat_w = Signal(dw)
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o_dat_we = Signal(dw//8)
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self.comb += If(selected,
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o_dat_w.eq(master.dat_w),
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o_dat_we.eq(master.dat_we)
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)
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dat_w_maskselect.append(o_dat_w)
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dat_we_maskselect.append(o_dat_we)
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self.comb += [
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controller.dat_w.eq(optree("|", dat_w_maskselect)),
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controller.dat_we.eq(optree("|", dat_we_maskselect))
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]
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# route data reads
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if controller_bits:
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for master in self.masters:
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controller_sel = Signal(controller_bits)
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for nc, controller in enumerate(controllers):
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for nb in range(nbanks):
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bank = getattr(controller, "bank"+str(nb))
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self.comb += If(bank.stb & bank.ack, controller_sel.eq(nc))
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for i in range(read_latency):
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n_controller_sel = Signal(controller_bits)
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self.sync += n_controller_sel.eq(controller_sel)
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controller_sel = n_controller_sel
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self.comb += master.dat_r.eq(Array(controllers)[controller_sel].dat_r)
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else:
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self.comb += [master.dat_r.eq(controllers[0].dat_r) for master in self.masters]
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def _split_master_addresses(self, controller_bits, bank_bits, rca_bits, cba_shift):
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m_ca = [] # controller address
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m_ba = [] # bank address
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m_rca = [] # row and column address
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for master in self.masters:
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cba = Signal(controller_bits + bank_bits)
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rca = Signal(rca_bits)
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cba_upper = cba_shift + controller_bits + bank_bits
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self.comb += cba.eq(master.adr[cba_shift:cba_upper])
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if cba_shift < rca_bits:
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self.comb += rca.eq(Cat(master.adr[:cba_shift], master.adr[cba_upper:]))
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else:
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self.comb += rca.eq(master.adr[:cba_shift])
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if controller_bits:
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ca = Signal(controller_bits)
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ba = Signal(bank_bits)
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self.comb += Cat(ba, ca).eq(cba)
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else:
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ca = None
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ba = cba
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m_ca.append(ca)
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m_ba.append(ba)
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m_rca.append(rca)
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return m_ca, m_ba, m_rca
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class Initiator(Module):
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def __init__(self, generator, bus):
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self.generator = generator
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self.bus = bus
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self.transaction_start = 0
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self.transaction = None
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self.transaction_end = None
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self.done = False
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def do_simulation(self, s):
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s.wr(self.bus.dat_w, 0)
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s.wr(self.bus.dat_we, 0)
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if not self.done:
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if self.transaction is not None and s.rd(self.bus.ack):
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s.wr(self.bus.stb, 0)
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if isinstance(self.transaction, TRead):
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self.transaction_end = s.cycle_counter + self.bus.read_latency
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else:
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self.transaction_end = s.cycle_counter + self.bus.write_latency - 1
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if self.transaction is None or s.cycle_counter == self.transaction_end:
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if self.transaction is not None:
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self.transaction.latency = s.cycle_counter - self.transaction_start - 1
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if isinstance(self.transaction, TRead):
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self.transaction.data = s.rd(self.bus.dat_r)
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else:
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s.wr(self.bus.dat_w, self.transaction.data)
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s.wr(self.bus.dat_we, self.transaction.sel)
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try:
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self.transaction = next(self.generator)
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except StopIteration:
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self.done = True
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self.transaction = None
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if self.transaction is not None:
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self.transaction_start = s.cycle_counter
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s.wr(self.bus.stb, 1)
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s.wr(self.bus.adr, self.transaction.address)
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if isinstance(self.transaction, TRead):
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s.wr(self.bus.we, 0)
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else:
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s.wr(self.bus.we, 1)
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class TargetModel:
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def __init__(self):
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self.last_bank = 0
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def read(self, bank, address):
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return 0
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def write(self, bank, address, data, we):
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pass
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# Round-robin scheduling
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def select_bank(self, pending_banks):
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if not pending_banks:
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return -1
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self.last_bank += 1
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if self.last_bank > max(pending_banks):
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self.last_bank = 0
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while self.last_bank not in pending_banks:
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self.last_bank += 1
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return self.last_bank
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class Target(Module):
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def __init__(self, model, *ifargs, **ifkwargs):
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self.model = model
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self.bus = Interface(*ifargs, **ifkwargs)
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self.rd_pipeline = [None]*self.bus.read_latency
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self.wr_pipeline = [None]*(self.bus.write_latency + 1)
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def do_simulation(self, s):
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# determine banks with pending requests
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pending_banks = set()
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for nb in range(self.bus.nbanks):
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bank = getattr(self.bus, "bank"+str(nb))
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if s.rd(bank.stb) and not s.rd(bank.ack):
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pending_banks.add(nb)
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# issue new transactions
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selected_bank_n = self.model.select_bank(pending_banks)
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for nb in range(self.bus.nbanks):
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bank = getattr(self.bus, "bank"+str(nb))
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if nb == selected_bank_n:
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s.wr(bank.ack, 1)
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else:
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s.wr(bank.ack, 0)
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rd_transaction = None
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wr_transaction = None
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if selected_bank_n >= 0:
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selected_bank = getattr(self.bus, "bank"+str(selected_bank_n))
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if s.rd(selected_bank.we):
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wr_transaction = selected_bank_n, s.rd(selected_bank.adr)
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else:
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rd_transaction = selected_bank_n, s.rd(selected_bank.adr)
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# data pipeline
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self.rd_pipeline.append(rd_transaction)
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self.wr_pipeline.append(wr_transaction)
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done_rd_transaction = self.rd_pipeline.pop(0)
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done_wr_transaction = self.wr_pipeline.pop(0)
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if done_rd_transaction is not None:
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s.wr(self.bus.dat_r, self.model.read(done_rd_transaction[0], done_rd_transaction[1]))
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if done_wr_transaction is not None:
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self.model.write(done_wr_transaction[0], done_wr_transaction[1],
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s.rd(self.bus.dat_w), s.rd(self.bus.dat_we))
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