litex/litex/gen
2022-05-09 17:53:27 +02:00
..
fhdl gen/fhdl/namer: Minor cleanup to ease readability. 2022-05-09 17:53:27 +02:00
sim gen/fhdl: Integrate namer from Migen to give us more flexibility on generated verilog names. 2022-05-06 16:04:24 +02:00
__init__.py
common.py gen: add specify SPDX License identifier and specify file is part of Migen and has been modified/adapted for LiteX. 2020-08-23 15:19:46 +02:00