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litex/migen/fhdl
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Sebastien Bourdeauducq 7a06e9457c Lowering of Special expressions + support ClockSignal/ResetSignal 2013-03-18 18:36:50 +01:00
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__init__.py Initial import, FHDL basic structure, divider example 2011-12-04 16:44:38 +01:00
module.py Lowering of Special expressions + support ClockSignal/ResetSignal 2013-03-18 18:36:50 +01:00
namer.py New 'specials' API 2013-02-22 17:56:35 +01:00
specials.py Lowering of Special expressions + support ClockSignal/ResetSignal 2013-03-18 18:36:50 +01:00
structure.py Lowering of Special expressions + support ClockSignal/ResetSignal 2013-03-18 18:36:50 +01:00
tools.py Lowering of Special expressions + support ClockSignal/ResetSignal 2013-03-18 18:36:50 +01:00
tracer.py bank: automatic register naming 2013-03-12 15:45:24 +01:00
verilog.py Lowering of Special expressions + support ClockSignal/ResetSignal 2013-03-18 18:36:50 +01:00
visit.py Lowering of Special expressions + support ClockSignal/ResetSignal 2013-03-18 18:36:50 +01:00